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1ca081000a
Bootargs for devices in the realtek target were previously consolidated in commitaf2cfbda2b("realtek: Consolidate bootargs"), since all devices currently use the same arguments. Commita75b9e3ecb("realtek: Adding RTL930X sub-target") reverted this without any argumentation, so let's undo that. Commit0b8dfe0851("realtek: Add RTL931X sub-target") introduced the old bootargs also for RTL931x, without providing any actual device support. Until that is done, let's assume vendors will have done what they did before, and use a baud rate of 115200. Fixes:a75b9e3ecb("realtek: Adding RTL930X sub-target") Signed-off-by: Sander Vanheule <sander@svanheule.net>
182 lines
3.5 KiB
Plaintext
182 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency = <1000000000>;
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cpu@0 {
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compatible = "mti,interaptive";
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reg = <0>;
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};
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cpu@1 {
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compatible = "mti,interaptive";
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reg = <1>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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lx_clk: lx_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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cpuclock: cpuclock@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* FIXME: there should be way to detect this */
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clock-frequency = <1000000000>;
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};
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cpuintc: cpuintc {
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compatible = "mti,cpu-interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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gic: interrupt-controller@1ddc0000 {
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compatible = "mti,gic";
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reg = <0x1ddc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpuintc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&cpuclock>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x18000000 0x10000>;
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spi0: spi@1200 {
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status = "okay";
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compatible = "realtek,rtl8380-spi";
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reg = <0x1200 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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watchdog0: watchdog@3260 {
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compatible = "realtek,rtl9310-wdt";
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reg = <0x3260 0xc>;
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realtek,reset-mode = "soc";
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clocks = <&lx_clk>;
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timeout-sec = <30>;
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interrupt-parent = <&gic>;
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interrupt-names = "phase1", "phase2";
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interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio0: gpio-controller@3300 {
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compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio";
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reg = <0x3300 0x1c>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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uart0: uart@2000 {
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compatible = "ns16550a";
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reg = <0x2000 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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uart1: uart@2100 {
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compatible = "ns16550a";
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reg = <0x2100 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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status = "disabled";
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};
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};
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ethernet0: ethernet@1b00a300 {
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status = "okay";
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compatible = "realtek,rtl838x-eth";
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reg = <0x1b00a300 0x100>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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switch0: switch@1b000000 {
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compatible = "realtek,rtl83xx-switch";
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status = "okay";
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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interrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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