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https://github.com/openwrt/openwrt.git
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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
113 lines
3.5 KiB
Diff
113 lines
3.5 KiB
Diff
From 4df4f114c9a91d94e0e9356261e1b149146852ea Mon Sep 17 00:00:00 2001
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From: Sean Young <sean@mess.org>
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Date: Wed, 20 Dec 2023 14:24:25 +0000
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Subject: [PATCH 0941/1085] pwm: bcm2835: Allow PWM driver to be used in atomic
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context
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commit fcc76072935935082efa127b97c7ddd880d2d793 upstream.
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clk_get_rate() may do a mutex lock. Fetch the clock rate once, and prevent
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rate changes using clk_rate_exclusive_get().
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Signed-off-by: Sean Young <sean@mess.org>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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---
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drivers/pwm/pwm-bcm2835.c | 38 +++++++++++++++++++++++++++++---------
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1 file changed, 29 insertions(+), 9 deletions(-)
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--- a/drivers/pwm/pwm-bcm2835.c
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+++ b/drivers/pwm/pwm-bcm2835.c
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@@ -28,6 +28,7 @@ struct bcm2835_pwm {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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+ unsigned long rate;
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};
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static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
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@@ -63,17 +64,11 @@ static int bcm2835_pwm_apply(struct pwm_
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{
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struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
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- unsigned long rate = clk_get_rate(pc->clk);
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unsigned long long period_cycles;
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u64 max_period;
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u32 val;
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- if (!rate) {
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- dev_err(pc->dev, "failed to get clock rate\n");
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- return -EINVAL;
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- }
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-
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/*
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* period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
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* must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
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@@ -88,13 +83,13 @@ static int bcm2835_pwm_apply(struct pwm_
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* <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
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* <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
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*/
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- max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, rate) - 1;
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+ max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
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if (state->period > max_period)
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return -EINVAL;
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/* set period */
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- period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * rate, NSEC_PER_SEC);
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+ period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
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/* don't accept a period that is too small */
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if (period_cycles < PERIOD_MIN)
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@@ -103,7 +98,7 @@ static int bcm2835_pwm_apply(struct pwm_
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writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
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/* set duty cycle */
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- val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * rate, NSEC_PER_SEC);
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+ val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
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writel(val, pc->base + DUTY(pwm->hwpwm));
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/* set polarity */
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@@ -132,6 +127,13 @@ static const struct pwm_ops bcm2835_pwm_
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.owner = THIS_MODULE,
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};
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+static void devm_clk_rate_exclusive_put(void *data)
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+{
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+ struct clk *clk = data;
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+
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+ clk_rate_exclusive_put(clk);
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+}
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+
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static int bcm2835_pwm_probe(struct platform_device *pdev)
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{
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struct bcm2835_pwm *pc;
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@@ -152,8 +154,26 @@ static int bcm2835_pwm_probe(struct plat
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
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"clock not found\n");
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+ ret = clk_rate_exclusive_get(pc->clk);
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+ if (ret)
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+ return dev_err_probe(&pdev->dev, ret,
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+ "fail to get exclusive rate\n");
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+
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+ ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put,
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+ pc->clk);
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+ if (ret) {
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+ clk_rate_exclusive_put(pc->clk);
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+ return ret;
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+ }
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+
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+ pc->rate = clk_get_rate(pc->clk);
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+ if (!pc->rate)
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+ return dev_err_probe(&pdev->dev, -EINVAL,
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+ "failed to get clock rate\n");
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+
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &bcm2835_pwm_ops;
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+ pc->chip.atomic = true;
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pc->chip.npwm = 2;
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ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
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