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572ea68070
Import pending patches adding support for MT7988 and provide builds for the reference board for all possible boot media. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
126 lines
3.4 KiB
Diff
126 lines
3.4 KiB
Diff
From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 19 Jul 2023 17:16:15 +0800
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Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981
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MT7981 actually uses MediaTek I2C controller v3 instead of v1.
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This patch adds support for I2C controller v3 fix fixes the I2C usability
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for MT7981.
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++--
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1 file changed, 43 insertions(+), 2 deletions(-)
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--- a/drivers/i2c/mtk_i2c.c
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+++ b/drivers/i2c/mtk_i2c.c
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@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = {
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[REG_DCM_EN] = 0xf88,
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};
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+static const uint mt_i2c_regs_v3[] = {
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+ [REG_PORT] = 0x0,
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+ [REG_INTR_MASK] = 0x8,
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+ [REG_INTR_STAT] = 0xc,
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+ [REG_CONTROL] = 0x10,
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+ [REG_TRANSFER_LEN] = 0x14,
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+ [REG_TRANSAC_LEN] = 0x18,
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+ [REG_DELAY_LEN] = 0x1c,
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+ [REG_TIMING] = 0x20,
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+ [REG_START] = 0x24,
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+ [REG_EXT_CONF] = 0x28,
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+ [REG_LTIMING] = 0x2c,
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+ [REG_HS] = 0x30,
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+ [REG_IO_CONFIG] = 0x34,
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+ [REG_FIFO_ADDR_CLR] = 0x38,
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+ [REG_TRANSFER_LEN_AUX] = 0x44,
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+ [REG_CLOCK_DIV] = 0x48,
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+ [REG_SOFTRESET] = 0x50,
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+ [REG_SLAVE_ADDR] = 0x94,
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+ [REG_DEBUGSTAT] = 0xe4,
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+ [REG_DEBUGCTRL] = 0xe8,
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+ [REG_FIFO_STAT] = 0xf4,
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+ [REG_FIFO_THRESH] = 0xf8,
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+ [REG_DCM_EN] = 0xf88,
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+};
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+
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struct mtk_i2c_soc_data {
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const uint *regs;
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uint dma_sync: 1;
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+ uint ltiming_adjust: 1;
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};
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struct mtk_i2c_priv {
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@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev
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(sample_cnt << HS_SAMPLE_OFFSET) |
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(step_cnt << HS_STEP_OFFSET);
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i2c_writel(priv, REG_HS, high_speed_reg);
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+ if (priv->soc_data->ltiming_adjust) {
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+ timing_reg = (sample_cnt << 12) | (step_cnt << 9);
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+ i2c_writel(priv, REG_LTIMING, timing_reg);
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+ }
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} else {
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ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
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&step_cnt, &sample_cnt);
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@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev
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high_speed_reg = I2C_TIME_CLR_VALUE;
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i2c_writel(priv, REG_TIMING, timing_reg);
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i2c_writel(priv, REG_HS, high_speed_reg);
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+ if (priv->soc_data->ltiming_adjust) {
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+ timing_reg = (sample_cnt << 6) | step_cnt;
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+ i2c_writel(priv, REG_LTIMING, timing_reg);
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+ }
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}
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+
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exit:
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if (mtk_i2c_clk_disable(priv))
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return log_msg_ret("set_speed disable clk", -1);
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@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice
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return log_msg_ret("probe enable clk", -1);
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mtk_i2c_init_hw(priv);
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-
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if (mtk_i2c_clk_disable(priv))
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return log_msg_ret("probe disable clk", -1);
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@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic
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static const struct mtk_i2c_soc_data mt76xx_soc_data = {
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.regs = mt_i2c_regs_v1,
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.dma_sync = 0,
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+ .ltiming_adjust = 0,
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};
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static const struct mtk_i2c_soc_data mt7981_soc_data = {
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- .regs = mt_i2c_regs_v1,
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+ .regs = mt_i2c_regs_v3,
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.dma_sync = 1,
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+ .ltiming_adjust = 1,
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};
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static const struct mtk_i2c_soc_data mt7986_soc_data = {
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.regs = mt_i2c_regs_v1,
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.dma_sync = 1,
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+ .ltiming_adjust = 0,
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};
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static const struct mtk_i2c_soc_data mt8183_soc_data = {
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.regs = mt_i2c_regs_v2,
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.dma_sync = 1,
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+ .ltiming_adjust = 0,
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};
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static const struct mtk_i2c_soc_data mt8518_soc_data = {
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.regs = mt_i2c_regs_v1,
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.dma_sync = 0,
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+ .ltiming_adjust = 0,
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};
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static const struct mtk_i2c_soc_data mt8512_soc_data = {
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.regs = mt_i2c_regs_v1,
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.dma_sync = 1,
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+ .ltiming_adjust = 0,
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};
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static const struct dm_i2c_ops mtk_i2c_ops = {
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