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https://github.com/openwrt/openwrt.git
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e5445333f6
Refreshed all patches. Remove upstreamed (superseded): - 950-0726-can-mcp251x-Allow-more-time-after-a-reset.patch Compile-tested on: brcm2708, cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
143 lines
4.5 KiB
Diff
143 lines
4.5 KiB
Diff
From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 23 Dec 2018 18:06:53 +0100
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Subject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo
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Many MIPS CPUs have optional CPU features which are not activates for
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all CPU cores. Print the CPU options which are implemented in the core
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in /proc/cpuinfo. This makes it possible to see what features are
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supported and which are not supported. This should cover all standard
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MIPS extensions, before it only printed information about the main MIPS
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ASEs.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 116 insertions(+)
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--- a/arch/mips/kernel/proc.c
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+++ b/arch/mips/kernel/proc.c
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@@ -134,6 +134,122 @@ static int show_cpuinfo(struct seq_file
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seq_printf(m, "micromips kernel\t: %s\n",
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(read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
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}
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+
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+ seq_printf(m, "Options implemented\t:");
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+ if (cpu_has_tlb)
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+ seq_printf(m, "%s", " tlb");
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+ if (cpu_has_ftlb)
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+ seq_printf(m, "%s", " ftlb");
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+ if (cpu_has_tlbinv)
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+ seq_printf(m, "%s", " tlbinv");
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+ if (cpu_has_segments)
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+ seq_printf(m, "%s", " segments");
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+ if (cpu_has_rixiex)
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+ seq_printf(m, "%s", " rixiex");
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+ if (cpu_has_ldpte)
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+ seq_printf(m, "%s", " ldpte");
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+ if (cpu_has_maar)
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+ seq_printf(m, "%s", " maar");
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+ if (cpu_has_rw_llb)
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+ seq_printf(m, "%s", " rw_llb");
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+ if (cpu_has_4kex)
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+ seq_printf(m, "%s", " 4kex");
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+ if (cpu_has_3k_cache)
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+ seq_printf(m, "%s", " 3k_cache");
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+ if (cpu_has_4k_cache)
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+ seq_printf(m, "%s", " 4k_cache");
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+ if (cpu_has_6k_cache)
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+ seq_printf(m, "%s", " 6k_cache");
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+ if (cpu_has_8k_cache)
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+ seq_printf(m, "%s", " 8k_cache");
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+ if (cpu_has_tx39_cache)
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+ seq_printf(m, "%s", " tx39_cache");
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+ if (cpu_has_octeon_cache)
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+ seq_printf(m, "%s", " octeon_cache");
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+ if (cpu_has_fpu)
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+ seq_printf(m, "%s", " fpu");
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+ if (cpu_has_32fpr)
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+ seq_printf(m, "%s", " 32fpr");
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+ if (cpu_has_cache_cdex_p)
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+ seq_printf(m, "%s", " cache_cdex_p");
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+ if (cpu_has_cache_cdex_s)
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+ seq_printf(m, "%s", " cache_cdex_s");
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+ if (cpu_has_prefetch)
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+ seq_printf(m, "%s", " prefetch");
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+ if (cpu_has_mcheck)
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+ seq_printf(m, "%s", " mcheck");
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+ if (cpu_has_ejtag)
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+ seq_printf(m, "%s", " ejtag");
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+ if (cpu_has_llsc)
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+ seq_printf(m, "%s", " llsc");
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+ if (cpu_has_bp_ghist)
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+ seq_printf(m, "%s", " bp_ghist");
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+ if (cpu_has_guestctl0ext)
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+ seq_printf(m, "%s", " guestctl0ext");
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+ if (cpu_has_guestctl1)
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+ seq_printf(m, "%s", " guestctl1");
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+ if (cpu_has_guestctl2)
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+ seq_printf(m, "%s", " guestctl2");
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+ if (cpu_has_guestid)
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+ seq_printf(m, "%s", " guestid");
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+ if (cpu_has_drg)
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+ seq_printf(m, "%s", " drg");
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+ if (cpu_has_rixi)
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+ seq_printf(m, "%s", " rixi");
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+ if (cpu_has_lpa)
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+ seq_printf(m, "%s", " lpa");
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+ if (cpu_has_mvh)
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+ seq_printf(m, "%s", " mvh");
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+ if (cpu_has_vtag_icache)
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+ seq_printf(m, "%s", " vtag_icache");
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+ if (cpu_has_dc_aliases)
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+ seq_printf(m, "%s", " dc_aliases");
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+ if (cpu_has_ic_fills_f_dc)
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+ seq_printf(m, "%s", " ic_fills_f_dc");
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+ if (cpu_has_pindexed_dcache)
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+ seq_printf(m, "%s", " pindexed_dcache");
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+ if (cpu_has_userlocal)
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+ seq_printf(m, "%s", " userlocal");
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+ if (cpu_has_nofpuex)
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+ seq_printf(m, "%s", " nofpuex");
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+ if (cpu_has_vint)
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+ seq_printf(m, "%s", " vint");
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+ if (cpu_has_veic)
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+ seq_printf(m, "%s", " veic");
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+ if (cpu_has_inclusive_pcaches)
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+ seq_printf(m, "%s", " inclusive_pcaches");
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+ if (cpu_has_perf_cntr_intr_bit)
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+ seq_printf(m, "%s", " perf_cntr_intr_bit");
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+ if (cpu_has_ufr)
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+ seq_printf(m, "%s", " ufr");
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+ if (cpu_has_fre)
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+ seq_printf(m, "%s", " fre");
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+ if (cpu_has_cdmm)
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+ seq_printf(m, "%s", " cdmm");
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+ if (cpu_has_small_pages)
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+ seq_printf(m, "%s", " small_pages");
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+ if (cpu_has_nan_legacy)
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+ seq_printf(m, "%s", " nan_legacy");
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+ if (cpu_has_nan_2008)
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+ seq_printf(m, "%s", " nan_2008");
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+ if (cpu_has_ebase_wg)
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+ seq_printf(m, "%s", " ebase_wg");
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+ if (cpu_has_badinstr)
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+ seq_printf(m, "%s", " badinstr");
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+ if (cpu_has_badinstrp)
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+ seq_printf(m, "%s", " badinstrp");
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+ if (cpu_has_contextconfig)
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+ seq_printf(m, "%s", " contextconfig");
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+ if (cpu_has_perf)
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+ seq_printf(m, "%s", " perf");
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+ if (cpu_has_shared_ftlb_ram)
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+ seq_printf(m, "%s", " shared_ftlb_ram");
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+ if (cpu_has_shared_ftlb_entries)
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+ seq_printf(m, "%s", " shared_ftlb_entries");
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+ if (cpu_has_mipsmt_pertccounters)
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+ seq_printf(m, "%s", " mipsmt_pertccounters");
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+ seq_printf(m, "\n");
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+
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seq_printf(m, "shadow register sets\t: %d\n",
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cpu_data[n].srsets);
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seq_printf(m, "kscratch registers\t: %d\n",
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