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https://github.com/openwrt/openwrt.git
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f07e572f64
bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
127 lines
4.2 KiB
Diff
127 lines
4.2 KiB
Diff
From 8af8b61bf6b5689af9f29f0e04e57c832dad0406 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 7 Feb 2020 16:01:33 +0100
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Subject: [PATCH] clk: bcm: rpi: Create a data structure for the clocks
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So far the driver has really only been providing a single clock, and stored
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both the data associated to that clock in particular with the data
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associated to the "controller".
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Since we will change that in the future, let's decouple the clock data from
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the provider data.
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Cc: Michael Turquette <mturquette@baylibre.com>
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Cc: linux-clk@vger.kernel.org
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Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/clk/bcm/clk-raspberrypi.c | 40 ++++++++++++++++++++-----------
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1 file changed, 26 insertions(+), 14 deletions(-)
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--- a/drivers/clk/bcm/clk-raspberrypi.c
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+++ b/drivers/clk/bcm/clk-raspberrypi.c
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@@ -35,11 +35,15 @@ struct raspberrypi_clk {
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struct device *dev;
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struct rpi_firmware *firmware;
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struct platform_device *cpufreq;
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+};
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+
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+struct raspberrypi_clk_data {
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+ struct clk_hw hw;
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unsigned long min_rate;
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unsigned long max_rate;
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- struct clk_hw pllb;
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+ struct raspberrypi_clk *rpi;
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};
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/*
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@@ -83,8 +87,9 @@ static int raspberrypi_clock_property(st
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static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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+ struct raspberrypi_clk_data *data =
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+ container_of(hw, struct raspberrypi_clk_data, hw);
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+ struct raspberrypi_clk *rpi = data->rpi;
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u32 val = 0;
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int ret;
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@@ -101,8 +106,9 @@ static int raspberrypi_fw_pll_is_on(stru
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static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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+ struct raspberrypi_clk_data *data =
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+ container_of(hw, struct raspberrypi_clk_data, hw);
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+ struct raspberrypi_clk *rpi = data->rpi;
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u32 val = 0;
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int ret;
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@@ -119,8 +125,9 @@ static unsigned long raspberrypi_fw_pll_
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static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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+ struct raspberrypi_clk_data *data =
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+ container_of(hw, struct raspberrypi_clk_data, hw);
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+ struct raspberrypi_clk *rpi = data->rpi;
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u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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int ret;
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@@ -142,13 +149,13 @@ static int raspberrypi_fw_pll_set_rate(s
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static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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+ struct raspberrypi_clk_data *data =
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+ container_of(hw, struct raspberrypi_clk_data, hw);
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u64 div, final_rate;
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u32 ndiv, fdiv;
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/* We can't use req->rate directly as it would overflow */
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- final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
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+ final_rate = clamp(req->rate, data->min_rate, data->max_rate);
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div = (u64)final_rate << A2W_PLL_FRAC_BITS;
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do_div(div, req->best_parent_rate);
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@@ -173,10 +180,15 @@ static const struct clk_ops raspberrypi_
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static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
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{
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+ struct raspberrypi_clk_data *data;
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struct clk_init_data init = {};
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u32 min_rate = 0, max_rate = 0;
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int ret;
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+ data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
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+ if (!data)
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+ return -ENOMEM;
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+ data->rpi = rpi;
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/* All of the PLLs derive from the external oscillator. */
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init.parent_names = (const char *[]){ "osc" };
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@@ -215,12 +227,12 @@ static int raspberrypi_register_pllb(str
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dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
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min_rate, max_rate);
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- rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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- rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+ data->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+ data->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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- rpi->pllb.init = &init;
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+ data->hw.init = &init;
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- return devm_clk_hw_register(rpi->dev, &rpi->pllb);
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+ return devm_clk_hw_register(rpi->dev, &data->hw);
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}
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static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
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