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d11efa1428
BCM6358 requires further work due to its shared TLB. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 36526
97 lines
2.9 KiB
Diff
97 lines
2.9 KiB
Diff
From 1baec3216529f795905b6376f9c8e4f14b114ba2 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Fri, 26 Apr 2013 12:03:15 +0200
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Subject: [PATCH 11/13] MIPS: BCM63XX: wire up the second CPU's irq line
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It's hardwired to IRQ3, so we don't need to actually check the CPU id.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 40 ++++++++++++++++++++++++++++++++--------
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1 file changed, 32 insertions(+), 8 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -329,11 +329,15 @@ static void __internal_irq_mask_##width(
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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- u32 irq_mask_addr = get_irq_mask_addr(0); \
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+ int cpu; \
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\
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- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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- val &= ~(1 << bit); \
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- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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+ for_each_online_cpu(cpu) { \
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+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
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+ \
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+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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+ val &= ~(1 << bit); \
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+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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+ } \
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} \
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\
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static void __internal_irq_unmask_##width(unsigned int irq) \
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@@ -341,11 +345,15 @@ static void __internal_irq_unmask_##widt
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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- u32 irq_mask_addr = get_irq_mask_addr(0); \
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+ int cpu; \
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+ \
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+ for_each_online_cpu(cpu) { \
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+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
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\
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- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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- val |= (1 << bit); \
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- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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+ val |= (1 << bit); \
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+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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+ } \
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}
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BUILD_IPIC_INTERNAL(32);
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@@ -369,6 +377,10 @@ asmlinkage void plat_irq_dispatch(void)
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do_IRQ(1);
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if (cause & CAUSEF_IP2)
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dispatch_internal(0);
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+#ifdef CONFIG_SMP
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+ if (cause & CAUSEF_IP3)
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+ dispatch_internal(1);
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+#else
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if (!is_ext_irq_cascaded) {
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if (cause & CAUSEF_IP3)
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do_IRQ(IRQ_EXT_0);
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@@ -379,6 +391,7 @@ asmlinkage void plat_irq_dispatch(void)
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if (cause & CAUSEF_IP6)
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do_IRQ(IRQ_EXT_3);
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}
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+#endif
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} while (1);
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}
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@@ -598,6 +611,14 @@ static struct irqaction cpu_ip2_cascade_
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.flags = IRQF_NO_THREAD,
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};
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+#ifdef CONFIG_SMP
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+static struct irqaction cpu_ip3_cascade_action = {
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+ .handler = no_action,
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+ .name = "cascade_ip3",
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+ .flags = IRQF_NO_THREAD,
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+};
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+#endif
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+
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static struct irqaction cpu_ext_cascade_action = {
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.handler = no_action,
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.name = "cascade_extirq",
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@@ -624,4 +645,7 @@ void __init arch_init_irq(void)
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}
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
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+#ifdef CONFIG_SMP
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+ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
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+#endif
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}
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