mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 08:21:14 +00:00
162 lines
4.4 KiB
Diff
162 lines
4.4 KiB
Diff
--- a/arch/arm/boot/dts/imx6dl.dtsi
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+++ b/arch/arm/boot/dts/imx6dl.dtsi
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@@ -105,6 +105,95 @@
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};
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};
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+ gpmi-nand {
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+ pinctrl_gpmi_nand_1: gpmi-nand-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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+ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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+ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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+ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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+ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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+ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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+ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
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+ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
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+ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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+ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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+ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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+ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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+ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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+ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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+ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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+ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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+ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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+ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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+ MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
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+ >;
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+ };
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+
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+ /* No strobe */
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+ pinctrl_gpmi_nand_2: gpmi-nand-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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+ MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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+ MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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+ MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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+ MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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+ MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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+ MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
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+ MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
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+ MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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+ MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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+ MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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+ MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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+ MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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+ MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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+ MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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+ MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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+ MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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+ MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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+ >;
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+ };
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+ };
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+
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+ i2c1 {
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+ pinctrl_i2c1_1: i2c1grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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+ MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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+ >;
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+ };
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+ };
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+
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+ i2c2 {
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+ pinctrl_i2c2_1: i2c2grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
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+ MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
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+ >;
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+ };
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+ pinctrl_i2c2_2: i2c2grp-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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+ MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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+ >;
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+ };
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+ };
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+
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+ i2c3 {
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+ pinctrl_i2c3_1: i2c3grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
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+ MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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+ >;
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+ };
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+ pinctrl_i2c3_2: i2c3grp-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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+ MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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+ >;
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+ };
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+ };
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+
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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@@ -112,6 +201,36 @@
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MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
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>;
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};
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+ pinctrl_uart1_2: uart1grp-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
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+ MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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+
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+ uart2 {
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+ pinctrl_uart2_1: uart2grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
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+ MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
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+ >;
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+ };
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+ pinctrl_uart2_2: uart2grp-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
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+ MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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+
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+ uart3 {
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+ pinctrl_uart3_1: uart3grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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+ MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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+ >;
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+ };
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};
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uart4 {
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@@ -122,6 +241,15 @@
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>;
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};
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};
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+
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+ uart5 {
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+ pinctrl_uart5_1: uart5grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
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+ MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
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+ >;
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+ };
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+ };
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usbotg {
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pinctrl_usbotg_2: usbotggrp-2 {
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
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imx6q-arm2.dtb \
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imx6q-gw5400-a.dtb \
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imx6q-gw54xx.dtb \
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+ imx6dl-gw51xx.dtb \
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imx6q-sabreauto.dtb \
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imx6q-sabrelite.dtb \
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imx6q-sabresd.dtb \
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