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fa79baf4a6
Copy backport, hack, pending patch and config from 5.15 to 6.1. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
121 lines
3.9 KiB
Diff
121 lines
3.9 KiB
Diff
From de6e05097f7db066afb0ad4c88b730949f7b7749 Mon Sep 17 00:00:00 2001
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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Date: Tue, 4 Apr 2023 18:21:35 +0100
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Subject: [PATCH] nvmem: mtk-efuse: Support postprocessing for GPU speed
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binning data
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On some MediaTek SoCs GPU speed binning data is available for read
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in the SoC's eFuse array but it has a format that is incompatible
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with what the OPP API expects, as we read a number from 0 to 7 but
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opp-supported-hw is expecting a bitmask to enable an OPP entry:
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being what we read limited to 0-7, it's straightforward to simply
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convert the value to BIT(value) as a post-processing action.
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So, introduce post-processing support and enable it by evaluating
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the newly introduced platform data's `uses_post_processing` member,
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currently enabled only for MT8186.
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Link: https://lore.kernel.org/r/20230404172148.82422-28-srinivas.kandagatla@linaro.org
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/nvmem/mtk-efuse.c | 53 +++++++++++++++++++++++++++++++++++++--
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1 file changed, 51 insertions(+), 2 deletions(-)
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--- a/drivers/nvmem/mtk-efuse.c
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+++ b/drivers/nvmem/mtk-efuse.c
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@@ -10,6 +10,11 @@
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#include <linux/io.h>
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#include <linux/nvmem-provider.h>
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#include <linux/platform_device.h>
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+#include <linux/property.h>
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+
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+struct mtk_efuse_pdata {
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+ bool uses_post_processing;
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+};
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struct mtk_efuse_priv {
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void __iomem *base;
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@@ -29,6 +34,37 @@ static int mtk_reg_read(void *context,
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return 0;
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}
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+static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index,
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+ unsigned int offset, void *data, size_t bytes)
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+{
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+ u8 *val = data;
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+
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+ if (val[0] < 8)
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+ val[0] = BIT(val[0]);
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+
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+ return 0;
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+}
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+
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+static void mtk_efuse_fixup_cell_info(struct nvmem_device *nvmem,
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+ struct nvmem_layout *layout,
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+ struct nvmem_cell_info *cell)
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+{
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+ size_t sz = strlen(cell->name);
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+
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+ /*
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+ * On some SoCs, the GPU speedbin is not read as bitmask but as
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+ * a number with range [0-7] (max 3 bits): post process to use
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+ * it in OPP tables to describe supported-hw.
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+ */
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+ if (cell->nbits <= 3 &&
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+ strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0)
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+ cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
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+}
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+
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+static struct nvmem_layout mtk_efuse_layout = {
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+ .fixup_cell_info = mtk_efuse_fixup_cell_info,
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+};
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+
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static int mtk_efuse_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -36,6 +72,7 @@ static int mtk_efuse_probe(struct platfo
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struct nvmem_device *nvmem;
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struct nvmem_config econfig = {};
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struct mtk_efuse_priv *priv;
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+ const struct mtk_efuse_pdata *pdata;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@@ -45,20 +82,32 @@ static int mtk_efuse_probe(struct platfo
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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+ pdata = device_get_match_data(dev);
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econfig.stride = 1;
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econfig.word_size = 1;
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econfig.reg_read = mtk_reg_read;
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econfig.size = resource_size(res);
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econfig.priv = priv;
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econfig.dev = dev;
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+ if (pdata->uses_post_processing)
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+ econfig.layout = &mtk_efuse_layout;
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nvmem = devm_nvmem_register(dev, &econfig);
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return PTR_ERR_OR_ZERO(nvmem);
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}
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+static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
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+ .uses_post_processing = true,
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+};
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+
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+static const struct mtk_efuse_pdata mtk_efuse_pdata = {
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+ .uses_post_processing = false,
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+};
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+
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static const struct of_device_id mtk_efuse_of_match[] = {
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- { .compatible = "mediatek,mt8173-efuse",},
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- { .compatible = "mediatek,efuse",},
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+ { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
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+ { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
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+ { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
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{/* sentinel */},
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};
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MODULE_DEVICE_TABLE(of, mtk_efuse_of_match);
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