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36746893ac
Fix the issue of dts buswidth cannot be applied properly with spi driver. Fix the name of buswidth to bus-width in dts in order to fit the format in linux spi kernel[1] so that spi-tx-bus-width & spi-rx-bus-width can be parsed properly. [1] Documentation/devicetree/bindings/spi/spi-controller.yaml Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
158 lines
3.7 KiB
Diff
158 lines
3.7 KiB
Diff
From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
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From: Sam Shih <sam.shih@mediatek.com>
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Date: Fri, 18 Nov 2022 20:01:21 +0100
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Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
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This patch adds spi support for MT7986.
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++
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arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
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3 files changed, 98 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
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@@ -59,6 +59,20 @@
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};
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&pio {
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+ spi_flash_pins: spi-flash-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi0", "spi0_wp_hold";
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+ };
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+ };
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+
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+ spic_pins: spic-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi1_2";
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+ };
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+ };
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+
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uart1_pins: uart1-pins {
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mux {
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function = "uart";
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@@ -105,6 +119,27 @@
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};
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};
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_flash_pins>;
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+ cs-gpios = <0>, <0>;
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+ status = "okay";
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+ spi_nand: spi_nand@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ spi-max-frequency = <10000000>;
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+ spi-tx-bus-width = <4>;
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+ spi-rx-bus-width = <4>;
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+ };
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+};
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+
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+&spi1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spic_pins>;
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+ cs-gpios = <0>, <0>;
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+ status = "okay";
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+};
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+
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&switch {
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ports {
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#address-cells = <1>;
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--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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@@ -294,6 +294,34 @@
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status = "disabled";
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};
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+ spi0: spi@1100a000 {
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+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0 0x1100a000 0 0x100>;
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_SPI0_CK>,
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+ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@1100b000 {
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+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0 0x1100b000 0 0x100>;
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
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+ <&infracfg CLK_INFRA_SPI1_CK>,
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+ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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+ status = "disabled";
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+ };
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+
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
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@@ -100,6 +100,20 @@
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};
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&pio {
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+ spi_flash_pins: spi-flash-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi0", "spi0_wp_hold";
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+ };
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+ };
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+
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+ spic_pins: spic-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi1_2";
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+ };
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+ };
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+
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wf_2g_5g_pins: wf-2g-5g-pins {
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mux {
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function = "wifi";
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@@ -132,6 +146,27 @@
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};
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};
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_flash_pins>;
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+ cs-gpios = <0>, <0>;
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+ status = "okay";
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+ spi_nand: spi_nand@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ spi-max-frequency = <10000000>;
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+ spi-tx-bus-width = <4>;
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+ spi-rx-bus-width = <4>;
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+ };
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+};
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+
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+&spi1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spic_pins>;
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+ cs-gpios = <0>, <0>;
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+ status = "okay";
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+};
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+
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&uart0 {
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status = "okay";
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};
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