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https://github.com/openwrt/openwrt.git
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861efe158a
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
80 lines
2.8 KiB
Diff
80 lines
2.8 KiB
Diff
From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Thu, 27 Jan 2022 10:18:01 +0100
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Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
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structure
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Soon the SPI-NAND core will need a way to request a SPI controller to
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enable ECC support for a given operation. This is because of the
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pipelined integration of certain ECC engines, which are directly managed
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by the SPI controller itself.
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Introduce a spi_mem_op additional field for this purpose: ecc.
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So far this field is left unset and checked to be false by all
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the SPI controller drivers in their ->supports_op() hook, as they all
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call spi_mem_default_supports_op().
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Acked-by: Pratyush Yadav <p.yadav@ti.com>
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Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
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(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
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---
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drivers/spi/spi-mem.c | 5 +++++
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include/linux/spi/spi-mem.h | 4 ++++
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2 files changed, 9 insertions(+)
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diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
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index ed966d8129eb..f38ac31961c9 100644
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--- a/drivers/spi/spi-mem.c
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+++ b/drivers/spi/spi-mem.c
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@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
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return false;
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}
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+ if (op->data.ecc) {
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+ if (!spi_mem_controller_is_capable(ctlr, ecc))
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+ return false;
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+ }
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+
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return spi_mem_check_buswidth(mem, op);
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}
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EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
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diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
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index 4a1bfe689872..2ba044d0d5e5 100644
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--- a/include/linux/spi/spi-mem.h
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+++ b/include/linux/spi/spi-mem.h
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@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
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* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
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* @data.buswidth: number of IO lanes used to send/receive the data
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* @data.dtr: whether the data should be sent in DTR mode or not
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+ * @data.ecc: whether error correction is required or not
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* @data.dir: direction of the transfer
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* @data.nbytes: number of data bytes to send/receive. Can be zero if the
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* operation does not involve transferring data
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@@ -119,6 +120,7 @@ struct spi_mem_op {
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struct {
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u8 buswidth;
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u8 dtr : 1;
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+ u8 ecc : 1;
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enum spi_mem_data_dir dir;
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unsigned int nbytes;
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union {
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@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
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/**
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* struct spi_controller_mem_caps - SPI memory controller capabilities
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* @dtr: Supports DTR operations
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+ * @ecc: Supports operations with error correction
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*/
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struct spi_controller_mem_caps {
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bool dtr;
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+ bool ecc;
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};
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#define spi_mem_controller_is_capable(ctlr, cap) \
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--
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2.35.1
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