mirror of
https://github.com/openwrt/openwrt.git
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a47279154e
Manually rebased patches:
bcm27xx:
patches-5.4/950-0267-xhci-add-quirk-for-host-controllers-that-don-t-updat.patch
bcm53xx:
patches-5.4/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
layerscape:
patches-5.4/802-can-0025-can-flexcan-add-LPSR-mode-support-for-i.MX7D.patch
patches-5.4/808-i2c-0002-MLK-10893-i2c-imx-add-irqf_no_suspend.patch
patches-5.4/820-usb-0016-MLK-16735-usb-host-add-XHCI_CDNS_HOST-flag.patch
Removed since could be reverse-applied by quilt:
mediatek:
patches-5.4/0700-arm-dts-mt7623-add-missing-pause-for-switchport.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711, x86_64
Run-tested: ipq806x/R7800, x86_64
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
Tested-by: Curtis Deptuck <curtdept@me.com> [x86_64]
Rebase of 802-can-0025-can-flexcan-add-LPSR-mode-support-for-i.MX7D.patch
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
91 lines
3.2 KiB
Diff
91 lines
3.2 KiB
Diff
From 7bb9b7d36fa457a9fc463108d1228fd318891da4 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.org>
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Date: Thu, 11 Jul 2019 17:55:43 +0100
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Subject: [PATCH] xhci: add quirk for host controllers that don't
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update endpoint DCS
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Seen on a VLI VL805 PCIe to USB controller. For non-stream endpoints
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at least, if the xHC halts on a particular TRB due to an error then
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the DCS field in the Out Endpoint Context maintained by the hardware
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is not updated with the current cycle state.
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Using the quirk XHCI_EP_CTX_BROKEN_DCS and instead fetch the DCS bit
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from the TRB that the xHC stopped on.
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See: https://github.com/raspberrypi/linux/issues/3060
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
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---
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drivers/usb/host/xhci-pci.c | 4 +++-
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drivers/usb/host/xhci-ring.c | 26 +++++++++++++++++++++++++-
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drivers/usb/host/xhci.h | 1 +
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3 files changed, 29 insertions(+), 2 deletions(-)
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--- a/drivers/usb/host/xhci-pci.c
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+++ b/drivers/usb/host/xhci-pci.c
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@@ -253,8 +253,10 @@ static void xhci_pci_quirks(struct devic
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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if (pdev->vendor == PCI_VENDOR_ID_VIA &&
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- pdev->device == 0x3483)
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+ pdev->device == 0x3483) {
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xhci->quirks |= XHCI_LPM_SUPPORT;
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+ xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
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+ }
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
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--- a/drivers/usb/host/xhci-ring.c
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+++ b/drivers/usb/host/xhci-ring.c
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@@ -527,7 +527,10 @@ void xhci_find_new_dequeue_state(struct
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struct xhci_virt_ep *ep = &dev->eps[ep_index];
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struct xhci_ring *ep_ring;
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struct xhci_segment *new_seg;
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+ struct xhci_segment *halted_seg = NULL;
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union xhci_trb *new_deq;
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+ union xhci_trb *halted_trb;
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+ int index = 0;
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dma_addr_t addr;
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u64 hw_dequeue;
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bool cycle_found = false;
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@@ -565,7 +568,28 @@ void xhci_find_new_dequeue_state(struct
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hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
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new_seg = ep_ring->deq_seg;
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new_deq = ep_ring->dequeue;
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- state->new_cycle_state = hw_dequeue & 0x1;
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+
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+ /*
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+ * Quirk: xHC write-back of the DCS field in the hardware dequeue
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+ * pointer is wrong - use the cycle state of the TRB pointed to by
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+ * the dequeue pointer.
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+ */
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+ if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
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+ !(ep->ep_state & EP_HAS_STREAMS))
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+ halted_seg = trb_in_td(xhci, cur_td->start_seg,
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+ cur_td->first_trb, cur_td->last_trb,
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+ hw_dequeue & ~0xf, false);
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+ if (halted_seg) {
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+ index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
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+ sizeof(*halted_trb);
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+ halted_trb = &halted_seg->trbs[index];
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+ state->new_cycle_state = halted_trb->generic.field[3] & 0x1;
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+ xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
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+ (u8)(hw_dequeue & 0x1), index,
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+ state->new_cycle_state);
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+ } else {
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+ state->new_cycle_state = hw_dequeue & 0x1;
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+ }
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state->stream_id = stream_id;
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/*
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--- a/drivers/usb/host/xhci.h
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+++ b/drivers/usb/host/xhci.h
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@@ -1873,6 +1873,7 @@ struct xhci_hcd {
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#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
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#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
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#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
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+#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(36)
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#define XHCI_DISABLE_SPARSE BIT_ULL(38)
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unsigned int num_active_eps;
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