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49d66e0468
This harmonizes the device node names (and thus the image names, too) between subtargets of the mediatek target. So far, each subtarget has somewhat used its own naming scheme. Now, we use the vendor_device syntax there, too. Since DTS names have different patterns and the target only contains a few devices, this does not replace DEVICE_DTS by a calculated default value (like for other targets). SUPPORTED_DEVICES is adjusted based on the node rename where necessary, though it looks like for several older devices it was not set up correctly so far. While at it, this also changes the DTS name for u7623-02-emmc-512m to all-lower-case. Cc: John Crispin <john@phrozen.org> Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
397 lines
8.0 KiB
Diff
397 lines
8.0 KiB
Diff
From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
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From: Kristian Evensen <kristian.evensen@gmail.com>
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Date: Sun, 17 Jun 2018 14:41:47 +0200
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Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
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---
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arch/arm/boot/dts/Makefile | 1 +
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.../dts/mt7623a-unielec-u7623-02-emmc-512m.dts | 18 +
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.../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 366 +++++++++++++++++++++
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3 files changed, 385 insertions(+)
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create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
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create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -1193,6 +1193,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7623a-rfb-nand.dtb \
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mt7623n-rfb-emmc.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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+ mt7623a-unielec-u7623-02-emmc-512m.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512m.dts
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@@ -0,0 +1,18 @@
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+/*
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+ * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
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+ *
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+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+ */
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+
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+/dts-v1/;
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+#include "mt7623a-unielec-u7623-02-emmc.dtsi"
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+
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+/ {
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+ model = "UniElec U7623-02 eMMC (512M RAM)";
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+ compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
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+
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+ memory@80000000 {
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+ device_type = "memory";
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+ reg = <0 0x80000000 0 0x20000000>;
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
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@@ -0,0 +1,349 @@
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+/*
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+ * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
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+ *
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+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+ */
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+
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+#include <dt-bindings/input/input.h>
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+#include "mt7623.dtsi"
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+#include "mt6323.dtsi"
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+
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+/ {
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+ compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
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+
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+ aliases {
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+ serial2 = &uart2;
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+ };
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+
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+ chosen {
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+ bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
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+ stdout-path = "serial2:115200n8";
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+ };
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+
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+ cpus {
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+ cpu@0 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+ };
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+
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+ cpu@1 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+ };
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+
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+ cpu@2 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+ };
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+
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+ cpu@3 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+ };
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+ };
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+
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_5v: regulator-5v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-5V";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&key_pins_a>;
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+
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+ factory {
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+ label = "factory";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&pio 256 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&led_pins_unielec>;
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+
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+ led3 {
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+ label = "u7623-01:green:led3";
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+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
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+ default-state = "off";
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+ };
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+
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+ led4 {
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+ label = "u7623-01:green:led4";
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+ gpios = <&pio 15 GPIO_ACTIVE_LOW>;
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+ default-state = "off";
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+ };
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+ };
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+
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+ mt7530: switch@0 {
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+ compatible = "mediatek,mt7530";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+};
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+
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+&crypto {
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+ status = "okay";
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+};
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+
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+ð {
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+ status = "okay";
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+
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+ gmac0: mac@0 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <0>;
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+ phy-mode = "trgmii";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+
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+ mdio: mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ phy5: ethernet-phy@5 {
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+ reg = <5>;
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+ phy-mode = "rgmii-rxid";
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+ };
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+ };
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+};
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+
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+&mt7530 {
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+ compatible = "mediatek,mt7530";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+ pinctrl-names = "default";
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+ mediatek,mcm;
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+ resets = <ðsys 2>;
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+ reset-names = "mcm";
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+ core-supply = <&mt6323_vpa_reg>;
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+ io-supply = <&mt6323_vemc3v3_reg>;
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+
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+ dsa,mii-bus = <&mdio>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan0";
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+ cpu = <&cpu_port0>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan1";
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+ cpu = <&cpu_port0>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan2";
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+ cpu = <&cpu_port0>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan3";
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+ cpu = <&cpu_port0>;
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "wan";
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+ cpu = <&cpu_port0>;
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+ };
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+
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+ cpu_port0: port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&gmac0>;
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+ phy-mode = "trgmii";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+ };
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+};
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+
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+&mmc0 {
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+ pinctrl-names = "default", "state_uhs";
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+ pinctrl-0 = <&mmc0_pins_default>;
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+ pinctrl-1 = <&mmc0_pins_uhs>;
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+ status = "okay";
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+ bus-width = <8>;
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+ max-frequency = <50000000>;
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+ cap-mmc-highspeed;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_1p8v>;
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+ non-removable;
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+};
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+
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+&pio {
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+ key_pins_a: keys-alt {
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+ pins-keys {
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+ pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
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+ <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
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+ input-enable;
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+ };
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+ };
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+
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+ led_pins_unielec: leds-unielec {
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+ pins-leds {
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+ pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
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+ <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
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+ };
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+ };
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+
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+ mmc0_pins_default: mmc0default {
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+ pins_cmd_dat {
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+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
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+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
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+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
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+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
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+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
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+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
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+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
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+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
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+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
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+ input-enable;
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+ bias-pull-up;
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+ };
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+
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+ pins_clk {
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+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
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+ bias-pull-down;
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+ };
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+
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+ pins_rst {
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+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ mmc0_pins_uhs: mmc0 {
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+ pins_cmd_dat {
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+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
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+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
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+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
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+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
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+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
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+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
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+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
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+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
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+ <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
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+ input-enable;
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+ drive-strength = <MTK_DRIVE_2mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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+ };
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+
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+ pins_clk {
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+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
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+ drive-strength = <MTK_DRIVE_2mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
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+ };
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+
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+ pins_rst {
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+ pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ pcie_default: pcie_pin_default {
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+ pins_cmd_dat {
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+ pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
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+ <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
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+ bias-disable;
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+ };
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+ };
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+};
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+
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+&pwm {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm_pins_a>;
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+ status = "okay";
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+};
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+
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+&pwrap {
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+ mt6323 {
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+ mt6323led: led {
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+ compatible = "mediatek,mt6323-led";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ led@0 {
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+ reg = <0>;
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+ label = "led0";
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+ default-state = "off";
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+ };
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+ };
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+ };
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+};
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+
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+&uart2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart2_pins_b>;
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ vusb33-supply = <®_3p3v>;
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+ vbus-supply = <®_3p3v>;
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+ status = "okay";
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+};
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+
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+&u3phy1 {
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+ status = "okay";
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+};
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+
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+&u3phy2 {
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+ status = "okay";
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+ mediatek,phy-switch = <&hifsys>;
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+};
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+
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_default>;
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+ status = "okay";
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+
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+ pcie@1,0 {
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+ status = "okay";
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+ };
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+
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+ pcie@2,0 {
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+ status = "okay";
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+ };
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+};
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+
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+&pcie1_phy {
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+ status = "okay";
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+};
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+
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