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335c1e7cfd
Without explicitly enabling sel_clk, clk_disable_unused() will disable it when boot is done, causing CPU hang on SPI1 register access on MT7986. Explicitly enable sel_clk to make SPI1 functional. Signed-off-by: Furong Xu <xfr@outlook.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
30 lines
860 B
Diff
30 lines
860 B
Diff
--- a/drivers/spi/spi-mt65xx.c
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+++ b/drivers/spi/spi-mt65xx.c
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@@ -1223,10 +1223,16 @@ static int mtk_spi_probe(struct platform
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goto err_disable_spi_hclk;
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}
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+ ret = clk_prepare_enable(mdata->sel_clk);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret);
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+ goto err_disable_spi_clk;
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+ }
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+
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ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
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- goto err_disable_spi_clk;
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+ goto err_disable_spi_sel_clk;
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}
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mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
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@@ -1277,6 +1283,8 @@ static int mtk_spi_probe(struct platform
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err_disable_runtime_pm:
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pm_runtime_disable(&pdev->dev);
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+err_disable_spi_sel_clk:
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+ clk_disable_unprepare(mdata->sel_clk);
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err_disable_spi_clk:
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clk_disable_unprepare(mdata->spi_clk);
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err_disable_spi_hclk:
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