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02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
127 lines
4.1 KiB
Diff
127 lines
4.1 KiB
Diff
From 5a58dbf4d82c29f7e6d89abc3520bed1aa2af05c Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Thu, 24 Apr 2014 11:31:20 -0500
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Subject: [PATCH 088/182] soc: qcom: Add device tree binding for GSBI
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Add device tree binding support for the QCOM GSBI driver.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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.../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78 ++++++++++++++++++++
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include/dt-bindings/soc/qcom,gsbi.h | 26 +++++++
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2 files changed, 104 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
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create mode 100644 include/dt-bindings/soc/qcom,gsbi.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
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@@ -0,0 +1,78 @@
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+QCOM GSBI (General Serial Bus Interface) Driver
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+
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+The GSBI controller is modeled as a node with zero or more child nodes, each
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+representing a serial sub-node device that is mux'd as part of the GSBI
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+configuration settings. The mode setting will govern the input/output mode of
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+the 4 GSBI IOs.
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+
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+Required properties:
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+- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
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+- reg: Address range for GSBI registers
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+- clocks: required clock
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+- clock-names: must contain "iface" entry
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+- qcom,mode : indicates MUX value for configuration of the serial interface.
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+ Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
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+
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+Optional properties:
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+- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
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+ dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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+
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+Required properties if child node exists:
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+- #address-cells: Must be 1
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+- #size-cells: Must be 1
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+- ranges: Must be present
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+
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+Properties for children:
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+
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+A GSBI controller node can contain 0 or more child nodes representing serial
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+devices. These serial devices can be a QCOM UART, I2C controller, spi
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+controller, or some combination of aforementioned devices.
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+
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+See the following for child node definitions:
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+Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
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+Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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+Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
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+
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+Example for APQ8064:
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+
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+#include <dt-bindings/soc/qcom,gsbi.h>
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+
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+ gsbi4@16300000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x16300000 0x100>;
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+ clocks = <&gcc GSBI4_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ qcom,crci = <GSBI_CRCI_QUP>;
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+
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+ /* child nodes go under here */
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+
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+ i2c_qup4: i2c@16380000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x16380000 0x1000>;
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+ interrupts = <0 153 0>;
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+
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+ clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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+ clock-names = "core", "iface";
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+
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+ clock-frequency = <200000>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ };
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+
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+ uart4: serial@16340000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x16340000 0x1000>,
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+ <0x16300000 0x1000>;
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+ interrupts = <0 152 0x0>;
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+ clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "ok";
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+ };
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+ };
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+
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--- /dev/null
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+++ b/include/dt-bindings/soc/qcom,gsbi.h
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@@ -0,0 +1,26 @@
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+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+#ifndef __DT_BINDINGS_QCOM_GSBI_H
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+#define __DT_BINDINGS_QCOM_GSBI_H
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+
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+#define GSBI_PROT_IDLE 0
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+#define GSBI_PROT_I2C_UIM 1
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+#define GSBI_PROT_I2C 2
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+#define GSBI_PROT_SPI 3
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+#define GSBI_PROT_UART_W_FC 4
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+#define GSBI_PROT_UIM 5
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+#define GSBI_PROT_I2C_UART 6
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+
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+#define GSBI_CRCI_QUP 0
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+#define GSBI_CRCI_UART 1
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+
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+#endif
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