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127 lines
2.9 KiB
C
127 lines
2.9 KiB
C
/*
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* Atheros AP94 reference board PCI initialization
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*
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* Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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struct ath9k_fixup {
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u16 *cal_data;
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unsigned slot;
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};
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static int ath9k_num_fixups;
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static struct ath9k_fixup ath9k_fixups[2];
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static void ath9k_pci_fixup(struct pci_dev *dev)
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{
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void __iomem *mem;
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u16 *cal_data = NULL;
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u16 cmd;
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u32 bar0;
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u32 val;
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unsigned i;
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for (i = 0; i < ath9k_num_fixups; i++) {
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if (ath9k_fixups[i].cal_data == NULL)
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continue;
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if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn))
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continue;
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cal_data = ath9k_fixups[i].cal_data;
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break;
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}
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if (cal_data == NULL)
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return;
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if (*cal_data != 0xa55a) {
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pr_err("pci %s: invalid calibration data\n", pci_name(dev));
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return;
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}
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pr_info("pci %s: fixup device configuration\n", pci_name(dev));
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mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
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if (!mem) {
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pr_err("pci %s: ioremap error\n", pci_name(dev));
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return;
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}
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
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switch (ath79_soc) {
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case ATH79_SOC_AR7161:
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
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AR71XX_PCI_MEM_BASE);
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break;
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case ATH79_SOC_AR7240:
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
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break;
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR7242:
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
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break;
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case ATH79_SOC_AR9344:
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
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break;
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default:
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BUG();
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}
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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/* set pointer to first reg address */
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cal_data += 3;
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while (*cal_data != 0xffff) {
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u32 reg;
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reg = *cal_data++;
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val = *cal_data++;
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val |= (*cal_data++) << 16;
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__raw_writel(val, mem + reg);
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udelay(100);
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}
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pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
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dev->vendor = val & 0xffff;
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dev->device = (val >> 16) & 0xffff;
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
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dev->revision = val & 0xff;
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dev->class = val >> 8; /* upper 3 bytes */
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
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iounmap(mem);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);
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void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data)
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{
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if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))
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return;
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ath9k_fixups[ath9k_num_fixups].slot = slot;
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ath9k_fixups[ath9k_num_fixups].cal_data = cal_data;
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ath9k_num_fixups++;
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}
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