mirror of
https://github.com/openwrt/openwrt.git
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258 lines
10 KiB
Diff
258 lines
10 KiB
Diff
--- a/gcc/config/arm/arm-cores.def
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+++ b/gcc/config/arm/arm-cores.def
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@@ -74,6 +74,7 @@ ARM_CORE("strongarm", strongarm, 4,
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ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
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ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
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ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
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+ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul)
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/* V4T Architecture Processors */
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ARM_CORE("arm7tdmi", arm7tdmi, 4T, FL_CO_PROC , fastmul)
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--- a/gcc/config/arm/arm.md
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+++ b/gcc/config/arm/arm.md
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@@ -435,7 +435,7 @@
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(define_attr "generic_sched" "yes,no"
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(const (if_then_else
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- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4")
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+ (ior (eq_attr "tune" "fa526,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4")
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(eq_attr "tune_cortexr4" "yes"))
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(const_string "no")
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(const_string "yes"))))
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@@ -467,6 +467,7 @@
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(include "arm1020e.md")
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(include "arm1026ejs.md")
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(include "arm1136jfs.md")
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+(include "fa526.md")
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(include "cortex-a5.md")
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(include "cortex-a8.md")
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(include "cortex-a9.md")
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--- a/gcc/config/arm/arm-tune.md
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+++ b/gcc/config/arm/arm-tune.md
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@@ -1,5 +1,5 @@
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;; -*- buffer-read-only: t -*-
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;; Generated automatically by gentune.sh from arm-cores.def
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(define_attr "tune"
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- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
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+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
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(const (symbol_ref "((enum attr_tune) arm_tune)")))
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--- a/gcc/config/arm/bpabi.h
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+++ b/gcc/config/arm/bpabi.h
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@@ -52,7 +52,8 @@
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/* The BPABI integer comparison routines return { -1, 0, 1 }. */
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#define TARGET_LIB_INT_CMP_BIASED !TARGET_BPABI
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-#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}"
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+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\
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+|march=armv4|mcpu=fa526:--fix-v4bx}"
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#define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}"
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--- /dev/null
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+++ b/gcc/config/arm/fa526.md
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@@ -0,0 +1,161 @@
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+;; Faraday FA526 Pipeline Description
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+;; Copyright (C) 2010 Free Software Foundation, Inc.
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+;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
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+
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+;; This file is part of GCC.
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+;;
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+;; GCC is free software; you can redistribute it and/or modify it under
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+;; the terms of the GNU General Public License as published by the Free
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+;; Software Foundation; either version 3, or (at your option) any later
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+;; version.
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+;;
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+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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+;; for more details.
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+;;
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+;; You should have received a copy of the GNU General Public License
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+;; along with GCC; see the file COPYING3. If not see
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+;; <http://www.gnu.org/licenses/>. */
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+
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+;; These descriptions are based on the information contained in the
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+;; FA526 Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
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+;;
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+;; Modeled pipeline characteristics:
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+;; LD -> any use: latency = 3 (2 cycle penalty).
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+;; ALU -> any use: latency = 2 (1 cycle penalty).
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+
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+;; This automaton provides a pipeline description for the Faraday
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+;; FA526 core.
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+;;
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+;; The model given here assumes that the condition for all conditional
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+;; instructions is "true", i.e., that all of the instructions are
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+;; actually executed.
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+
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+(define_automaton "fa526")
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+
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;; Pipelines
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+
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+;; There is a single pipeline
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+;;
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+;; The ALU pipeline has fetch, decode, execute, memory, and
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+;; write stages. We only need to model the execute, memory and write
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+;; stages.
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+
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+;; S E M W
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+
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+(define_cpu_unit "fa526_core" "fa526")
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+
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;; ALU Instructions
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+
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+;; ALU instructions require two cycles to execute, and use the ALU
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+;; pipeline in each of the three stages. The results are available
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+;; after the execute stage stage has finished.
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+;;
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+;; If the destination register is the PC, the pipelines are stalled
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+;; for several cycles. That case is not modeled here.
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+
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+;; ALU operations
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+(define_insn_reservation "526_alu_op" 1
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "alu"))
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+ "fa526_core")
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+
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+(define_insn_reservation "526_alu_shift_op" 2
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "alu_shift,alu_shift_reg"))
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+ "fa526_core")
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+
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;; Multiplication Instructions
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+
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+(define_insn_reservation "526_mult1" 2
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy"))
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+ "fa526_core")
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+
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+(define_insn_reservation "526_mult2" 5
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\
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+ umlals,smulls,smlals,smlawx"))
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+ "fa526_core*4")
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+
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;; Load/Store Instructions
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+
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+;; The models for load/store instructions do not accurately describe
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+;; the difference between operations with a base register writeback
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+;; (such as "ldm!"). These models assume that all memory references
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+;; hit in dcache.
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+
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+(define_insn_reservation "526_load1_op" 3
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "load1,load_byte"))
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+ "fa526_core")
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+
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+(define_insn_reservation "526_load2_op" 4
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "load2"))
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+ "fa526_core*2")
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+
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+(define_insn_reservation "526_load3_op" 5
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "load3"))
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+ "fa526_core*3")
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+
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+(define_insn_reservation "526_load4_op" 6
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "load4"))
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+ "fa526_core*4")
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+
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+(define_insn_reservation "526_store1_op" 0
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "store1"))
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+ "fa526_core")
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+
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+(define_insn_reservation "526_store2_op" 1
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "store2"))
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+ "fa526_core*2")
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+
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+(define_insn_reservation "526_store3_op" 2
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "store3"))
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+ "fa526_core*3")
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+
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+(define_insn_reservation "526_store4_op" 3
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "store4"))
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+ "fa526_core*4")
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+
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;; Branch and Call Instructions
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+
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+;; Branch instructions are difficult to model accurately. The FA526
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+;; core can predict most branches. If the branch is predicted
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+;; correctly, and predicted early enough, the branch can be completely
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+;; eliminated from the instruction stream. Some branches can
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+;; therefore appear to require zero cycle to execute. We assume that
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+;; all branches are predicted correctly, and that the latency is
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+;; therefore the minimum value.
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+
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+(define_insn_reservation "526_branch_op" 0
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "branch"))
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+ "fa526_core")
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+
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+;; The latency for a call is actually the latency when the result is available.
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+;; i.e. R0 ready for int return value. For most cases, the return value is set
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+;; by a mov instruction, which has 1 cycle latency.
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+(define_insn_reservation "526_call_op" 1
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+ (and (eq_attr "tune" "fa526")
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+ (eq_attr "type" "call"))
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+ "fa526_core")
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+
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--- a/gcc/config/arm/t-arm
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+++ b/gcc/config/arm/t-arm
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@@ -23,6 +23,7 @@ MD_INCLUDES= $(srcdir)/config/arm/arm-tu
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$(srcdir)/config/arm/arm-generic.md \
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$(srcdir)/config/arm/arm1020e.md \
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$(srcdir)/config/arm/arm1026ejs.md \
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+ $(srcdir)/config/arm/fa526.md \
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$(srcdir)/config/arm/arm1136jfs.md \
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$(srcdir)/config/arm/arm926ejs.md \
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$(srcdir)/config/arm/cirrus.md \
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--- a/gcc/config/arm/t-arm-elf
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+++ b/gcc/config/arm/t-arm-elf
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@@ -36,6 +36,10 @@ MULTILIB_DIRNAMES = arm thumb
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MULTILIB_EXCEPTIONS =
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MULTILIB_MATCHES =
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+#MULTILIB_OPTIONS += mcpu=fa526
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+#MULTILIB_DIRNAMES += fa526
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+#MULTILIB_EXCEPTIONS += *mthumb*/*mcpu=fa526
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+
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#MULTILIB_OPTIONS += march=armv7
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#MULTILIB_DIRNAMES += thumb2
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#MULTILIB_EXCEPTIONS += march=armv7* marm/*march=armv7*
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@@ -52,6 +56,7 @@ MULTILIB_MATCHES =
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MULTILIB_OPTIONS += mfloat-abi=hard
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MULTILIB_DIRNAMES += fpu
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MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard*
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+MULTILIB_EXCEPTIONS += *mcpu=fa526/*mfloat-abi=hard*
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# MULTILIB_OPTIONS += mcpu=ep9312
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# MULTILIB_DIRNAMES += ep9312
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--- a/gcc/doc/invoke.texi
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+++ b/gcc/doc/invoke.texi
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@@ -9923,7 +9923,8 @@ assembly code. Permissible names are: @
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@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3},
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@samp{cortex-m1},
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@samp{cortex-m0},
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-@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
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+@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
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+@samp{fa526}.
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@item -mtune=@var{name}
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@opindex mtune
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