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https://github.com/openwrt/openwrt.git
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8c6f00ef4f
Refresh patches.
Remove upstreamed patches:
- backport/096-mips-math-emu-Write-protect-delay-slot-emulation-pages.patch
- pending/510-f2fs-fix-sanity_check_raw_super-on-big-endian-machines.patch
- brcm2708/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch
Compile-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Runtime-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From 82f8b13481afeb2400bce276cf88a757fac87a21 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Fri, 14 Jul 2017 17:33:08 -0700
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Subject: [PATCH 131/454] drm/vc4: Fix pitch setup for T-format scanout.
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The documentation said to use src_w here, and I didn't consider that
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we actually needed to be using pitch somewhere in our setup. Fixes
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scanout on my DSI panel when X11 does initial setup with 1920x1080
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HDMI and 800x480 DSI both at 0,0 of the same framebuffer.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Fixes: 98830d91da08 ("drm/vc4: Add T-format scanout support.")
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 20 +++++++++++++++-----
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1 file changed, 15 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -547,14 +547,24 @@ static int vc4_plane_mode_set(struct drm
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tiling = SCALER_CTL0_TILING_LINEAR;
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pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
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break;
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- case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
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+
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+ case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
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+ /* For T-tiled, the FB pitch is "how many bytes from
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+ * one row to the next, such that pitch * tile_h ==
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+ * tile_size * tiles_per_row."
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+ */
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+ u32 tile_size_shift = 12;
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+ u32 tile_h_shift = 5;
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+ u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
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+
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tiling = SCALER_CTL0_TILING_256B_OR_T;
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- pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
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- VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
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- VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
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- SCALER_PITCH0_TILE_WIDTH_R));
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+ pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
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+ VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
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+ VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
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break;
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+ }
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+
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default:
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DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
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(long long)fb->modifier);
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