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084dfb8ebd
Refreshed all patches. Compile-tested on: ipq40xx, ramips Runtime-tested on: ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
69 lines
2.4 KiB
Diff
69 lines
2.4 KiB
Diff
From 29e154716049310bb8c559f742bf2b460d5b6bbc Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:38 +0800
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Subject: [PATCH 159/224] mmc: mediatek: improve eMMC hs400 mode read
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performance
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enlarge outstanding value to improve read performance
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -81,6 +81,7 @@
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC50_CFG0 0x208
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+#define EMMC50_CFG3 0x220
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#define SDC_FIFO_CFG 0x228
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/*--------------------------------------------------------------------------*/
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@@ -251,6 +252,8 @@
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#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
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#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
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+#define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
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+
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#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
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#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
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@@ -320,6 +323,7 @@ struct msdc_save_para {
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u32 pad_ds_tune;
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u32 pad_cmd_tune;
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u32 emmc50_cfg0;
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+ u32 emmc50_cfg3;
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u32 sdc_fifo_cfg;
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};
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@@ -1750,6 +1754,9 @@ static int msdc_prepare_hs400_tuning(str
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writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
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/* hs400 mode must set it to 0 */
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sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
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+ /* to improve read performance, set outstanding to 2 */
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+ sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
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+
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return 0;
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}
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@@ -2000,6 +2007,7 @@ static void msdc_save_reg(struct msdc_ho
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host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
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host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
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host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
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+ host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
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host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
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}
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@@ -2017,6 +2025,7 @@ static void msdc_restore_reg(struct msdc
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writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
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writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
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writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
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+ writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
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writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
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}
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