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14940aee45
Removed upstreamed: target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch The following patch does not apply to upstream any more and needs some more work to make it work fully again. I am not sure if we are still able to set the UART to a none standard baud rate. target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch These patches needed manually changes: target/linux/generic/pending-5.4/110-ehci_hcd_ignore_oc.patch target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch All others updated automatically. Compile-tested on: malta/le, armvirt/64, lantiq/xrx200 Runtime-tested on: malta/le, armvirt/64, lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Wed, 10 Apr 2019 08:00:47 -0700
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Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
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GPIO PERST#
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Gateworks boards use PLX PEX860x switches where downstream ports
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have their PERST# driven from the PEX GPIO.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -25,6 +25,7 @@
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#include <linux/ktime.h>
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#include <linux/mm.h>
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#include <linux/nvme.h>
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+#include <linux/of.h>
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#include <linux/platform_data/x86/apple.h>
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#include <linux/pm_runtime.h>
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#include <linux/suspend.h>
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@@ -5790,3 +5791,34 @@ static void nvidia_ion_ahci_fixup(struct
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pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
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+
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+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
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+/*
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+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
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+ * as they are used for slots1-7 PERST#
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+ */
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+static void newport_pciesw_early_fixup(struct pci_dev *dev)
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+{
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+ u32 dw;
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+
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+ if (!of_machine_is_compatible("gw,newport"))
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+ return;
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+
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+ if (dev->devfn != 0)
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+ return;
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+
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+ dev_info(&dev->dev, "de-asserting PERST#\n");
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+ pci_read_config_dword(dev, 0x62c, &dw);
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+ dw |= 0xaaa8; /* GPIO1-7 outputs */
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+ pci_write_config_dword(dev, 0x62c, dw);
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+
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+ pci_read_config_dword(dev, 0x644, &dw);
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+ dw |= 0xfe; /* GPIO1-7 output high */
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+ pci_write_config_dword(dev, 0x644, dw);
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+
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+ msleep(100);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
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+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */
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