mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
130 lines
5.0 KiB
Diff
130 lines
5.0 KiB
Diff
--- a/arch/mips/bcm47xx/nvram.c
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+++ b/arch/mips/bcm47xx/nvram.c
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@@ -50,6 +50,9 @@ static void early_nvram_init(void)
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#ifdef CONFIG_BCM47XX_BCMA
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case BCM47XX_BUS_TYPE_BCMA:
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bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
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+ if (bcma_cc->flash_type != BCMA_PFLASH)
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+ return;
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+
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base = bcma_cc->pflash.window;
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lim = bcma_cc->pflash.window_size;
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break;
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--- a/drivers/bcma/driver_mips.c
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+++ b/drivers/bcma/driver_mips.c
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@@ -189,6 +189,7 @@ static void bcma_core_mips_flash_detect(
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break;
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case BCMA_CC_FLASHT_PARA:
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pr_info("found parallel flash.\n");
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+ bus->drv_cc.flash_type = BCMA_PFLASH;
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bus->drv_cc.pflash.window = 0x1c000000;
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bus->drv_cc.pflash.window_size = 0x02000000;
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -117,10 +117,68 @@
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#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
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#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
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#define BCMA_CC_FLASHCTL 0x0040
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+
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+/* Start/busy bit in flashcontrol */
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+#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
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+#define BCMA_CC_FLASHCTL_ACTION 0x00000700
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+#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
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#define BCMA_CC_FLASHCTL_START 0x80000000
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#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
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+
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+/* flashcontrol action+opcodes for ST flashes */
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+#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
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+#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
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+#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
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+#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
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+#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
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+#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
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+#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
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+#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
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+#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
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+#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
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+#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
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+#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
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+
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+
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+/* flashcontrol action+opcodes for Atmel flashes */
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+#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
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+#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
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+#define BCMA_CC_FLASHCTL_AT_BUF1_READ
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+#define BCMA_CC_FLASHCTL_AT_BUF2_READ
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+#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
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+#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
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+#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
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+#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
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+#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
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+#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
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+#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
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+#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
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+#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
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+#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
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+#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
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+#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
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+#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
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+#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
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+#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
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+#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
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+#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
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+
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#define BCMA_CC_FLASHADDR 0x0044
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#define BCMA_CC_FLASHDATA 0x0048
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+
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+/* Status register bits for ST flashes */
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+#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
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+#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
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+#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
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+#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
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+#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
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+
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+/* Status register bits for Atmel flashes */
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+#define BCMA_CC_FLASHDATA_AT_READY 0x80
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+#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
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+#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
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+#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
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+
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#define BCMA_CC_BCAST_ADDR 0x0050
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#define BCMA_CC_BCAST_DATA 0x0054
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#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
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@@ -324,6 +382,12 @@
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#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
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#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
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+#define BCMA_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
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+#define BCMA_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
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+#define BCMA_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
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+#define BCMA_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
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+
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+
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/* Data for the PMU, if available.
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* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
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*/
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@@ -333,6 +397,10 @@ struct bcma_chipcommon_pmu {
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};
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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+enum bcma_flash_type {
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+ BCMA_PFLASH,
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+};
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+
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struct bcma_pflash {
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u8 buswidth;
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u32 window;
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@@ -358,7 +426,10 @@ struct bcma_drv_cc {
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u16 fast_pwrup_delay;
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struct bcma_chipcommon_pmu pmu;
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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- struct bcma_pflash pflash;
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+ enum bcma_flash_type flash_type;
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+ union {
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+ struct bcma_pflash pflash;
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+ };
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int nr_serial_ports;
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struct bcma_serial_port serial_ports[4];
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