mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-19 21:58:04 +00:00
d4b4bc98bb
Replace clock drivers for MT7988 with backported upstream commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
114 lines
3.3 KiB
Diff
114 lines
3.3 KiB
Diff
From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
|
Date: Sun, 19 Nov 2023 22:24:16 +0100
|
|
Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
|
|
to DT schema
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
DT schema helps validating DTS files. Binding was moved to clock/ as
|
|
this hardware is a clock provider. Example required a small fix for
|
|
"reg" value (1 address cell + 1 size cell).
|
|
|
|
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
|
Reviewed-by: Rob Herring <robh@kernel.org>
|
|
Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
|
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
---
|
|
.../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
|
|
.../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++
|
|
2 files changed, 54 insertions(+), 29 deletions(-)
|
|
delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
|
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
|
|
|
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
|
+++ /dev/null
|
|
@@ -1,29 +0,0 @@
|
|
-Mediatek ethsys controller
|
|
-============================
|
|
-
|
|
-The Mediatek ethsys controller provides various clocks to the system.
|
|
-
|
|
-Required Properties:
|
|
-
|
|
-- compatible: Should be:
|
|
- - "mediatek,mt2701-ethsys", "syscon"
|
|
- - "mediatek,mt7622-ethsys", "syscon"
|
|
- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
|
|
- - "mediatek,mt7629-ethsys", "syscon"
|
|
- - "mediatek,mt7981-ethsys", "syscon"
|
|
- - "mediatek,mt7986-ethsys", "syscon"
|
|
-- #clock-cells: Must be 1
|
|
-- #reset-cells: Must be 1
|
|
-
|
|
-The ethsys controller uses the common clk binding from
|
|
-Documentation/devicetree/bindings/clock/clock-bindings.txt
|
|
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
|
-
|
|
-Example:
|
|
-
|
|
-ethsys: clock-controller@1b000000 {
|
|
- compatible = "mediatek,mt2701-ethsys", "syscon";
|
|
- reg = <0 0x1b000000 0 0x1000>;
|
|
- #clock-cells = <1>;
|
|
- #reset-cells = <1>;
|
|
-};
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
|
@@ -0,0 +1,54 @@
|
|
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: Mediatek ethsys controller
|
|
+
|
|
+description:
|
|
+ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
|
+
|
|
+maintainers:
|
|
+ - James Liao <jamesjj.liao@mediatek.com>
|
|
+
|
|
+properties:
|
|
+ compatible:
|
|
+ oneOf:
|
|
+ - items:
|
|
+ - enum:
|
|
+ - mediatek,mt2701-ethsys
|
|
+ - mediatek,mt7622-ethsys
|
|
+ - mediatek,mt7629-ethsys
|
|
+ - mediatek,mt7981-ethsys
|
|
+ - mediatek,mt7986-ethsys
|
|
+ - const: syscon
|
|
+ - items:
|
|
+ - const: mediatek,mt7623-ethsys
|
|
+ - const: mediatek,mt2701-ethsys
|
|
+ - const: syscon
|
|
+
|
|
+ reg:
|
|
+ maxItems: 1
|
|
+
|
|
+ "#clock-cells":
|
|
+ const: 1
|
|
+
|
|
+ "#reset-cells":
|
|
+ const: 1
|
|
+
|
|
+required:
|
|
+ - reg
|
|
+ - "#clock-cells"
|
|
+ - "#reset-cells"
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ clock-controller@1b000000 {
|
|
+ compatible = "mediatek,mt2701-ethsys", "syscon";
|
|
+ reg = <0x1b000000 0x1000>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|