mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-19 21:58:04 +00:00
7af3b202d4
Import patch to make sure SGM_REG_SEL clock is always enabled as it seems that more registers than just SGMIISYS0 and SGMIISYS1 are depending on that clock being enabled. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
31 lines
1.4 KiB
Diff
31 lines
1.4 KiB
Diff
From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
|
|
From: Daniel Golle <daniel@makrotopia.org>
|
|
Date: Sun, 18 Feb 2024 01:59:59 +0000
|
|
Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
|
|
|
|
Without the SGM_REG_SEL clock enabled the system freezes if trying to
|
|
access registers used by MT7981 clock drivers itself.
|
|
Mark SGM_REG_SEL as critical to make sure it is always enabled to
|
|
prevent freezes on boot depending on probe order.
|
|
|
|
Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
|
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|
---
|
|
drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
|
|
1 file changed, 3 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
|
|
+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
|
|
@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
|
|
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
|
|
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
|
|
0x1C0, 21),
|
|
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
|
|
- 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
|
|
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
|
|
+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
|
|
+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
|
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
|
|
0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
|
|
/* CLK_CFG_6 */
|