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659f4a13dd
With Linux 6.1 many of our downstream patches and out-of-tree files can be removed or at least replaced by backported upstream commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org> [fix CMDLINE_OVERRIDE for arm64] Signed-off-by: Bjørn Mork <bjorn@mork.no>
119 lines
3.2 KiB
Diff
119 lines
3.2 KiB
Diff
From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
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From: Sam Shih <sam.shih@mediatek.com>
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Date: Fri, 6 Jan 2023 16:28:44 +0100
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Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
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This patch adds PCIe support for MT7986.
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Signed-off-by: Jieyy Yang <jieyy.yang@mediatek.com>
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
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arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++
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2 files changed, 68 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
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@@ -93,6 +93,15 @@
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non-removable;
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no-sd;
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no-sdio;
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+};
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+
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_pins>;
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+ status = "okay";
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+};
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+
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+&pcie_phy {
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status = "okay";
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};
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@@ -155,6 +164,13 @@
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};
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};
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+ pcie_pins: pcie-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
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+ };
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+ };
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+
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spi_flash_pins: spi-flash-pins {
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mux {
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function = "spi";
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--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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@@ -8,6 +8,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7986-clk.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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+#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "mediatek,mt7986a";
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@@ -360,6 +361,57 @@
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status = "disabled";
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};
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+ pcie: pcie@11280000 {
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+ compatible = "mediatek,mt7986-pcie",
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+ "mediatek,mt8192-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ reg = <0x00 0x11280000 0x00 0x4000>;
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+ reg-names = "pcie-mac";
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+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0x00 0x20000000 0x00
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+ 0x20000000 0x00 0x10000000>;
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+ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
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+ <&infracfg CLK_INFRA_IPCIE_CK>,
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+ <&infracfg CLK_INFRA_IPCIER_CK>,
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+ <&infracfg CLK_INFRA_IPCIEB_CK>;
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+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
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+ status = "disabled";
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+
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+ phys = <&pcie_port PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
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+ <0 0 0 2 &pcie_intc 1>,
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+ <0 0 0 3 &pcie_intc 2>,
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+ <0 0 0 4 &pcie_intc 3>;
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+ pcie_intc: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+
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+ pcie_phy: t-phy@11c00000 {
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+ compatible = "mediatek,mt7986-tphy",
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+ "mediatek,generic-tphy-v2";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ pcie_port: pcie-phy@11c00000 {
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+ reg = <0 0x11c00000 0 0x20000>;
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+ clocks = <&clk40m>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ };
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+ };
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+
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usb_phy: t-phy@11e10000 {
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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