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67d998e25d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.145
No patches needed a rebase.
23.05 backport:
Rebased patch mediatek/100-dts-update-mt7622-rfb1.patch due to
changes introduced in commit e37aa926447f ("arm64: dts: mediatek:
mt7622: fix memory node warning check") in version v5.15.143 and we
jumped over from v5.15.139 directly to v5.15.145.
Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3
23.05 backport:
Stijn:
Compile-tested: ath79/generic, ipq40xx/generic, mvebu/cortexa72, ramips/mt{7621,7620,76x8}, realtek/rtl{838x,930x}, 86/64.
Run-tested: cortexa72 (RB5009UG+S+IN), mt7621 (EAP615-Wall v1), rtl838x (GS1900-10HP, GS1900-8HP, GS108T v3).
Petr:
Compile-tested: ipq807x, mvebu/cortexa9
Run-tested: turris-omnia, prpl-haze
Tested-by: Stijn Segers <foss@volatilesystems.org> [23.05 testing]
Signed-off-by: John Audia <therealgraysky@proton.me>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [23.05 refresh]
(cherry picked from commit 8de4cc77a6)
47 lines
1.9 KiB
Diff
47 lines
1.9 KiB
Diff
From 8df9fefd1d04f6f97f6015d7347104f69e6ea580 Mon Sep 17 00:00:00 2001
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From: Baruch Siach <baruch.siach@siklu.com>
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Date: Tue, 21 Jun 2022 11:54:52 +0300
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Subject: [PATCH] PCI: dwc: Move GEN3_RELATED DBI definitions to common header
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These are common dwc macros that will be used for other platforms.
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Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il
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Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
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drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
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2 files changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-designware.h
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+++ b/drivers/pci/controller/dwc/pcie-designware.h
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@@ -74,6 +74,12 @@
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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+#define GEN3_RELATED_OFF 0x890
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+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
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+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
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+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
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+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
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+
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#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
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#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
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--- a/drivers/pci/controller/dwc/pcie-tegra194.c
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+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
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@@ -194,12 +194,6 @@
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#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
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#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
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-#define GEN3_RELATED_OFF 0x890
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-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
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-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
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-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
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-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
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-
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#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
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#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
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#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
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