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67d998e25d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.145
No patches needed a rebase.
23.05 backport:
Rebased patch mediatek/100-dts-update-mt7622-rfb1.patch due to
changes introduced in commit e37aa926447f ("arm64: dts: mediatek:
mt7622: fix memory node warning check") in version v5.15.143 and we
jumped over from v5.15.139 directly to v5.15.145.
Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3
23.05 backport:
Stijn:
Compile-tested: ath79/generic, ipq40xx/generic, mvebu/cortexa72, ramips/mt{7621,7620,76x8}, realtek/rtl{838x,930x}, 86/64.
Run-tested: cortexa72 (RB5009UG+S+IN), mt7621 (EAP615-Wall v1), rtl838x (GS1900-10HP, GS1900-8HP, GS108T v3).
Petr:
Compile-tested: ipq807x, mvebu/cortexa9
Run-tested: turris-omnia, prpl-haze
Tested-by: Stijn Segers <foss@volatilesystems.org> [23.05 testing]
Signed-off-by: John Audia <therealgraysky@proton.me>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [23.05 refresh]
(cherry picked from commit 8de4cc77a6)
53 lines
1.6 KiB
Diff
53 lines
1.6 KiB
Diff
From f91d0e8bd6c1f812bc2589050c05a90ee886c749 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 15 May 2022 23:00:42 +0200
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Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock
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The built-in PPE engine has a dedicated clock for the EIP-197 crypto
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engine.
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So, since the required clock currently missing add support for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
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---
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drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -3177,6 +3177,24 @@ static struct clk_branch gcc_nss_ptp_ref
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},
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};
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+static struct clk_branch gcc_crypto_ppe_clk = {
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+ .halt_reg = 0x68310,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x68310,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_crypto_ppe_clk",
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+ .parent_names = (const char *[]){
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+ "nss_ppe_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_branch gcc_nssnoc_ce_apb_clk = {
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.halt_reg = 0x6830c,
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.clkr = {
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@@ -4649,6 +4667,7 @@ static struct clk_regmap *gcc_ipq8074_cl
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[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
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[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
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[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
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+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq8074_resets[] = {
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