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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From a9f7dc27469ca9588d7aa572bdfdfd5f0f1aab6a Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Thu, 26 May 2022 22:42:47 +0200
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Subject: [PATCH] arm64: dts: qcom: adjust whitespace around '='
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Fix whitespace coding style: use single space instead of tabs or
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multiple spaces around '=' sign in property assignment. No functional
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changes (same DTB).
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -119,7 +119,7 @@
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<&xo>;
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clock-names = "aux", "cfg_ahb", "ref";
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- resets = <&gcc GCC_USB1_PHY_BCR>,
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+ resets = <&gcc GCC_USB1_PHY_BCR>,
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<&gcc GCC_USB3PHY_1_PHY_BCR>;
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reset-names = "phy","common";
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status = "disabled";
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@@ -162,7 +162,7 @@
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<&xo>;
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clock-names = "aux", "cfg_ahb", "ref";
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- resets = <&gcc GCC_USB0_PHY_BCR>,
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+ resets = <&gcc GCC_USB0_PHY_BCR>,
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<&gcc GCC_USB3PHY_0_PHY_BCR>;
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reset-names = "phy","common";
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status = "disabled";
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