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8c6f00ef4f
Refresh patches.
Remove upstreamed patches:
- backport/096-mips-math-emu-Write-protect-delay-slot-emulation-pages.patch
- pending/510-f2fs-fix-sanity_check_raw_super-on-big-endian-machines.patch
- brcm2708/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch
Compile-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Runtime-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
81 lines
2.5 KiB
Diff
81 lines
2.5 KiB
Diff
From e27613dee9bede1a5d8c86c3cdc5244175651534 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Wed, 24 Jun 2015 14:10:44 +0100
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Subject: [PATCH 012/454] spi-bcm2835: Support pin groups other than 7-11
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The spi-bcm2835 driver automatically uses GPIO chip-selects due to
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some unreliability of the native ones. In doing so it chooses the
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same pins as the native chip-selects would use, but the existing
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code always uses pins 7 and 8, wherever the SPI function is mapped.
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Search the pinctrl group assigned to the driver for pins that
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correspond to native chip-selects, and use those for GPIO chip-
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selects.
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/spi/spi-bcm2835.c | 45 ++++++++++++++++++++++++++++++++-------
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1 file changed, 37 insertions(+), 8 deletions(-)
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--- a/drivers/spi/spi-bcm2835.c
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+++ b/drivers/spi/spi-bcm2835.c
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@@ -686,6 +686,8 @@ static int bcm2835_spi_setup(struct spi_
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{
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int err;
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struct gpio_chip *chip;
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+ struct device_node *pins;
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+ u32 pingroup_index;
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/*
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* sanity checking the native-chipselects
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*/
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@@ -702,15 +704,42 @@ static int bcm2835_spi_setup(struct spi_
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"setup: only two native chip-selects are supported\n");
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return -EINVAL;
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}
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- /* now translate native cs to GPIO */
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- /* get the gpio chip for the base */
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- chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
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- if (!chip)
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- return 0;
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+ /* now translate native cs to GPIO */
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+ /* first look for chip select pins in the devices pin groups */
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+ for (pingroup_index = 0;
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+ (pins = of_parse_phandle(spi->master->dev.of_node,
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+ "pinctrl-0",
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+ pingroup_index)) != 0;
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+ pingroup_index++) {
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+ u32 pin;
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+ u32 pin_index;
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+ for (pin_index = 0;
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+ of_property_read_u32_index(pins,
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+ "brcm,pins",
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+ pin_index,
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+ &pin) == 0;
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+ pin_index++) {
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+ if (((spi->chip_select == 0) &&
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+ ((pin == 8) || (pin == 36) || (pin == 46))) ||
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+ ((spi->chip_select == 1) &&
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+ ((pin == 7) || (pin == 35)))) {
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+ spi->cs_gpio = pin;
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+ break;
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+ }
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+ }
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+ of_node_put(pins);
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+ }
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+ /* if that fails, assume GPIOs 7-11 are used */
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+ if (!gpio_is_valid(spi->cs_gpio) ) {
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+ /* get the gpio chip for the base */
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+ chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
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+ if (!chip)
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+ return 0;
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- /* and calculate the real CS */
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- spi->cs_gpio = chip->base + 8 - spi->chip_select;
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+ /* and calculate the real CS */
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+ spi->cs_gpio = chip->base + 8 - spi->chip_select;
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+ }
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/* and set up the "mode" and level */
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dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
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