mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
89 lines
3.0 KiB
Diff
89 lines
3.0 KiB
Diff
--- a/arch/cris/arch-v10/drivers/axisflashmap.c
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+++ b/arch/cris/arch-v10/drivers/axisflashmap.c
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@@ -113,7 +113,7 @@ static struct map_info map_cse1 = {
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/* If no partition-table was found, we use this default-set. */
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#define MAX_PARTITIONS 7
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-#define NUM_DEFAULT_PARTITIONS 3
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+#define NUM_DEFAULT_PARTITIONS 2
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/*
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* Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the
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@@ -122,19 +122,14 @@ static struct map_info map_cse1 = {
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*/
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static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
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{
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- .name = "boot firmware",
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- .size = CONFIG_ETRAX_PTABLE_SECTOR,
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- .offset = 0
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- },
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- {
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.name = "kernel",
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- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR),
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- .offset = CONFIG_ETRAX_PTABLE_SECTOR
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+ .size = 0x00,
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+ .offset = 0
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},
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{
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- .name = "filesystem",
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- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR,
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- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR)
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+ .name = "rootfs",
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+ .size = 0x200000,
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+ .offset = 0x200000
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}
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};
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@@ -281,6 +276,11 @@ static int __init init_axis_flash(void)
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struct partitiontable_entry *ptable;
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int use_default_ptable = 1; /* Until proven otherwise. */
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const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n";
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+ unsigned int kernel_part_size = 0;
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+ unsigned char *flash_mem = (unsigned char*)(FLASH_CACHED_ADDR);
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+ unsigned int flash_scan_count = 0;
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+ const char *part_magic = "ACME_PART_MAGIC";
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+ unsigned int magic_len = strlen(part_magic);
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if (!(mymtd = flash_probe())) {
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/* There's no reason to use this module if no flash chip can
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@@ -293,6 +293,31 @@ static int __init init_axis_flash(void)
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axisflash_mtd = mymtd;
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}
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+ /* scan flash to findout where out partition starts */
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+
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+ printk(KERN_INFO "Scanning flash for end of kernel magic\n");
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+ for(flash_scan_count = 0; flash_scan_count < 100000; flash_scan_count++) {
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+ if(strncmp(&flash_mem[flash_scan_count], part_magic, magic_len - 1) == 0) {
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+ kernel_part_size = flash_mem[flash_scan_count + magic_len ];
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+ kernel_part_size <<= 8;
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+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 2];
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+ kernel_part_size <<= 8;
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+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 1];
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+ kernel_part_size <<= 8;
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+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 3];
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+ printk(KERN_INFO "Kernel ends at 0x%.08X\n", kernel_part_size);
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+ flash_scan_count = 1100000;
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+ }
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+ }
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+
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+
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+ if(kernel_part_size){
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+ kernel_part_size = (kernel_part_size & 0xffff0000);
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+ axis_default_partitions[0].size = kernel_part_size;
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+ axis_default_partitions[1].size = mymtd->size - axis_default_partitions[0].size;
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+ axis_default_partitions[1].offset = axis_default_partitions[0].size;
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+ }
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+
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if (mymtd) {
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mymtd->owner = THIS_MODULE;
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ptable_head = (struct partitiontable_head *)(FLASH_CACHED_ADDR +
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--- a/arch/cris/arch-v10/lib/hw_settings.S
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+++ b/arch/cris/arch-v10/lib/hw_settings.S
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@@ -60,3 +60,5 @@
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.dword R_PORT_PB_SET
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.dword PB_SET_VALUE
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.dword 0 ; No more register values
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+ .ascii "ACME_PART_MAGIC"
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+ .dword 0xdeadc0de
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