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64afcbad3d
It will be used on NanoPi R2C and OrangePi R1 Plus LTS board. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
303 lines
8.6 KiB
Diff
303 lines
8.6 KiB
Diff
From 4ac94f728a588e7096dd5010cd7141a309ea7805 Mon Sep 17 00:00:00 2001
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From: Frank Sae <Frank.Sae@motor-comm.com>
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Date: Thu, 2 Feb 2023 11:00:37 +0800
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Subject: [PATCH] net: phy: Add driver for Motorcomm yt8531 gigabit ethernet
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phy
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Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
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verified the driver on AM335x platform with yt8531 board. On the
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board, yt8531 gigabit ethernet phy works in utp mode, RGMII
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interface, supports 1000M/100M/10M speeds, and wol(magic package).
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Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/Kconfig | 2 +-
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drivers/net/phy/motorcomm.c | 208 +++++++++++++++++++++++++++++++++++-
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2 files changed, 207 insertions(+), 3 deletions(-)
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
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tristate "Motorcomm PHYs"
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help
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Enables support for Motorcomm network PHYs.
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- Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs.
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+ Currently supports YT85xx Gigabit Ethernet PHYs.
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config NATIONAL_PHY
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tristate "National Semiconductor PHYs"
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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- * Motorcomm 8511/8521/8531S PHY driver.
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+ * Motorcomm 8511/8521/8531/8531S PHY driver.
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*
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* Author: Peter Geis <pgwipeout@gmail.com>
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* Author: Frank <Frank.Sae@motor-comm.com>
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@@ -14,6 +14,7 @@
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#define PHY_ID_YT8511 0x0000010a
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#define PHY_ID_YT8521 0x0000011a
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+#define PHY_ID_YT8531 0x4f51e91b
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#define PHY_ID_YT8531S 0x4f51e91a
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/* YT8521/YT8531S Register Overview
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@@ -517,6 +518,61 @@ err_restore_page:
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return phy_restore_page(phydev, old_page, ret);
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}
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+static int yt8531_set_wol(struct phy_device *phydev,
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+ struct ethtool_wolinfo *wol)
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+{
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+ const u16 mac_addr_reg[] = {
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+ YTPHY_WOL_MACADDR2_REG,
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+ YTPHY_WOL_MACADDR1_REG,
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+ YTPHY_WOL_MACADDR0_REG,
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+ };
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+ const u8 *mac_addr;
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+ u16 mask, val;
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+ int ret;
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+ u8 i;
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+
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+ if (wol->wolopts & WAKE_MAGIC) {
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+ mac_addr = phydev->attached_dev->dev_addr;
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+
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+ /* Store the device address for the magic packet */
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+ for (i = 0; i < 3; i++) {
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+ ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i],
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+ ((mac_addr[i * 2] << 8)) |
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+ (mac_addr[i * 2 + 1]));
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ /* Enable WOL feature */
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+ mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
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+ val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
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+ val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
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+ ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
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+ mask, val);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Enable WOL interrupt */
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+ ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
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+ YTPHY_IER_WOL);
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+ if (ret < 0)
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+ return ret;
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+ } else {
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+ /* Disable WOL feature */
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+ mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
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+ ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
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+ mask, 0);
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+
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+ /* Disable WOL interrupt */
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+ ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
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+ YTPHY_IER_WOL, 0);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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static int yt8511_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, YT8511_PAGE_SELECT);
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@@ -767,6 +823,17 @@ static int ytphy_rgmii_clk_delay_config(
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return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val);
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}
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+static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ phy_lock_mdio_bus(phydev);
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+ ret = ytphy_rgmii_clk_delay_config(phydev);
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+ phy_unlock_mdio_bus(phydev);
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+
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+ return ret;
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+}
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+
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/**
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* yt8521_probe() - read chip config then set suitable polling_mode
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* @phydev: a pointer to a &struct phy_device
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@@ -891,6 +958,43 @@ static int yt8521_probe(struct phy_devic
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val);
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}
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+static int yt8531_probe(struct phy_device *phydev)
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+{
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+ struct device_node *node = phydev->mdio.dev.of_node;
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+ u16 mask, val;
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+ u32 freq;
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+
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+ if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
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+ freq = YTPHY_DTS_OUTPUT_CLK_DIS;
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+
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+ switch (freq) {
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+ case YTPHY_DTS_OUTPUT_CLK_DIS:
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+ mask = YT8531_SCR_SYNCE_ENABLE;
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+ val = 0;
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+ break;
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+ case YTPHY_DTS_OUTPUT_CLK_25M:
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+ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
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+ YT8531_SCR_CLK_FRE_SEL_125M;
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+ val = YT8531_SCR_SYNCE_ENABLE |
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+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
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+ YT8531_SCR_CLK_SRC_REF_25M);
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+ break;
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+ case YTPHY_DTS_OUTPUT_CLK_125M:
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+ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
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+ YT8531_SCR_CLK_FRE_SEL_125M;
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+ val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
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+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
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+ YT8531_SCR_CLK_SRC_PLL_125M);
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+ break;
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+ default:
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+ phydev_warn(phydev, "Freq err:%u\n", freq);
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+ return -EINVAL;
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+ }
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+
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+ return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
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+ val);
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+}
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+
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/**
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* ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
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* @phydev: a pointer to a &struct phy_device
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@@ -1387,6 +1491,94 @@ err_restore_page:
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return phy_restore_page(phydev, old_page, ret);
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}
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+static int yt8531_config_init(struct phy_device *phydev)
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+{
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+ struct device_node *node = phydev->mdio.dev.of_node;
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+ int ret;
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+
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+ ret = ytphy_rgmii_clk_delay_config_with_lock(phydev);
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+ if (ret < 0)
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+ return ret;
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+
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+ if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
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+ /* disable auto sleep */
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+ ret = ytphy_modify_ext_with_lock(phydev,
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+ YT8521_EXTREG_SLEEP_CONTROL1_REG,
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+ YT8521_ESC1R_SLEEP_SW, 0);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
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+ /* enable RXC clock when no wire plug */
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+ ret = ytphy_modify_ext_with_lock(phydev,
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+ YT8521_CLOCK_GATING_REG,
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+ YT8521_CGR_RX_CLK_EN, 0);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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+ * yt8531_link_change_notify() - Adjust the tx clock direction according to
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+ * the current speed and dts config.
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+ * @phydev: a pointer to a &struct phy_device
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+ *
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+ * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please
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+ * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not
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+ * JH7110.
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+ */
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+static void yt8531_link_change_notify(struct phy_device *phydev)
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+{
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+ struct device_node *node = phydev->mdio.dev.of_node;
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+ bool tx_clk_adj_enabled = false;
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+ bool tx_clk_1000_inverted;
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+ bool tx_clk_100_inverted;
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+ bool tx_clk_10_inverted;
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+ u16 val = 0;
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+ int ret;
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+
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+ if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled"))
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+ tx_clk_adj_enabled = true;
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+
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+ if (!tx_clk_adj_enabled)
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+ return;
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+
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+ if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted"))
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+ tx_clk_10_inverted = true;
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+ if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted"))
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+ tx_clk_100_inverted = true;
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+ if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted"))
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+ tx_clk_1000_inverted = true;
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+
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+ if (phydev->speed < 0)
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+ return;
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+
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+ switch (phydev->speed) {
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+ case SPEED_1000:
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+ if (tx_clk_1000_inverted)
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+ val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
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+ break;
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+ case SPEED_100:
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+ if (tx_clk_100_inverted)
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+ val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
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+ break;
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+ case SPEED_10:
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+ if (tx_clk_10_inverted)
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+ val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG,
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+ YT8521_RC1R_TX_CLK_SEL_INVERTED, val);
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+ if (ret < 0)
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+ phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret);
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+}
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+
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/**
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* yt8521_prepare_fiber_features() - A small helper function that setup
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* fiber's features.
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@@ -1970,6 +2162,17 @@ static struct phy_driver motorcomm_phy_d
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.resume = yt8521_resume,
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},
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{
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+ PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
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+ .name = "YT8531 Gigabit Ethernet",
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+ .probe = yt8531_probe,
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+ .config_init = yt8531_config_init,
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+ .suspend = genphy_suspend,
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+ .resume = genphy_resume,
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+ .get_wol = ytphy_get_wol,
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+ .set_wol = yt8531_set_wol,
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+ .link_change_notify = yt8531_link_change_notify,
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+ },
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+ {
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PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
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.name = "YT8531S Gigabit Ethernet",
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.get_features = yt8521_get_features,
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@@ -1990,7 +2193,7 @@ static struct phy_driver motorcomm_phy_d
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module_phy_driver(motorcomm_phy_drvs);
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-MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver");
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+MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver");
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MODULE_AUTHOR("Peter Geis");
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MODULE_AUTHOR("Frank");
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MODULE_LICENSE("GPL");
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@@ -1998,6 +2201,7 @@ MODULE_LICENSE("GPL");
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static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
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+ { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
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{ /* sentinel */ }
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};
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