mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 17:18:59 +00:00
7ace30aeb6
Backport upstream code split patch for qca8k needed for ipq40xx target to correctly implement a DSA driver. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
136 lines
4.6 KiB
Diff
136 lines
4.6 KiB
Diff
From d5f901eab2e9dfed1095995dfc98f231f4fd2971 Mon Sep 17 00:00:00 2001
|
|
From: Christian Marangi <ansuelsmth@gmail.com>
|
|
Date: Wed, 27 Jul 2022 13:35:13 +0200
|
|
Subject: [PATCH 04/14] net: dsa: qca8k: move qca8k read/write/rmw and reg
|
|
table to common code
|
|
|
|
The same reg table and read/write/rmw function are used by drivers
|
|
based on qca8k family switch.
|
|
Move them to common code to make it accessible also by other drivers.
|
|
|
|
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
|
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
|
|
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
|
---
|
|
drivers/net/dsa/qca/qca8k-8xxx.c | 42 ------------------------------
|
|
drivers/net/dsa/qca/qca8k-common.c | 38 +++++++++++++++++++++++++++
|
|
drivers/net/dsa/qca/qca8k.h | 6 +++++
|
|
3 files changed, 44 insertions(+), 42 deletions(-)
|
|
|
|
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
|
|
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
|
|
@@ -133,24 +133,6 @@ qca8k_set_page(struct qca8k_priv *priv,
|
|
return 0;
|
|
}
|
|
|
|
-static int
|
|
-qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
|
|
-{
|
|
- return regmap_read(priv->regmap, reg, val);
|
|
-}
|
|
-
|
|
-static int
|
|
-qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
|
|
-{
|
|
- return regmap_write(priv->regmap, reg, val);
|
|
-}
|
|
-
|
|
-static int
|
|
-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
|
|
-{
|
|
- return regmap_update_bits(priv->regmap, reg, mask, write_val);
|
|
-}
|
|
-
|
|
static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
|
|
{
|
|
struct qca8k_mgmt_eth_data *mgmt_eth_data;
|
|
@@ -483,30 +465,6 @@ exit:
|
|
return ret;
|
|
}
|
|
|
|
-static const struct regmap_range qca8k_readable_ranges[] = {
|
|
- regmap_reg_range(0x0000, 0x00e4), /* Global control */
|
|
- regmap_reg_range(0x0100, 0x0168), /* EEE control */
|
|
- regmap_reg_range(0x0200, 0x0270), /* Parser control */
|
|
- regmap_reg_range(0x0400, 0x0454), /* ACL */
|
|
- regmap_reg_range(0x0600, 0x0718), /* Lookup */
|
|
- regmap_reg_range(0x0800, 0x0b70), /* QM */
|
|
- regmap_reg_range(0x0c00, 0x0c80), /* PKT */
|
|
- regmap_reg_range(0x0e00, 0x0e98), /* L3 */
|
|
- regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
|
|
- regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
|
|
- regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
|
|
- regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
|
|
- regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
|
|
- regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
|
|
- regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
|
|
-
|
|
-};
|
|
-
|
|
-static const struct regmap_access_table qca8k_readable_table = {
|
|
- .yes_ranges = qca8k_readable_ranges,
|
|
- .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
|
|
-};
|
|
-
|
|
static struct regmap_config qca8k_regmap_config = {
|
|
.reg_bits = 16,
|
|
.val_bits = 32,
|
|
--- a/drivers/net/dsa/qca/qca8k-common.c
|
|
+++ b/drivers/net/dsa/qca/qca8k-common.c
|
|
@@ -61,3 +61,41 @@ const struct qca8k_mib_desc ar8327_mib[]
|
|
MIB_DESC(1, 0xa8, "RXUnicast"),
|
|
MIB_DESC(1, 0xac, "TXUnicast"),
|
|
};
|
|
+
|
|
+int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
|
|
+{
|
|
+ return regmap_read(priv->regmap, reg, val);
|
|
+}
|
|
+
|
|
+int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
|
|
+{
|
|
+ return regmap_write(priv->regmap, reg, val);
|
|
+}
|
|
+
|
|
+int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
|
|
+{
|
|
+ return regmap_update_bits(priv->regmap, reg, mask, write_val);
|
|
+}
|
|
+
|
|
+static const struct regmap_range qca8k_readable_ranges[] = {
|
|
+ regmap_reg_range(0x0000, 0x00e4), /* Global control */
|
|
+ regmap_reg_range(0x0100, 0x0168), /* EEE control */
|
|
+ regmap_reg_range(0x0200, 0x0270), /* Parser control */
|
|
+ regmap_reg_range(0x0400, 0x0454), /* ACL */
|
|
+ regmap_reg_range(0x0600, 0x0718), /* Lookup */
|
|
+ regmap_reg_range(0x0800, 0x0b70), /* QM */
|
|
+ regmap_reg_range(0x0c00, 0x0c80), /* PKT */
|
|
+ regmap_reg_range(0x0e00, 0x0e98), /* L3 */
|
|
+ regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
|
|
+ regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
|
|
+ regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
|
|
+ regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
|
|
+ regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
|
|
+ regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
|
|
+ regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
|
|
+};
|
|
+
|
|
+const struct regmap_access_table qca8k_readable_table = {
|
|
+ .yes_ranges = qca8k_readable_ranges,
|
|
+ .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
|
|
+};
|
|
--- a/drivers/net/dsa/qca/qca8k.h
|
|
+++ b/drivers/net/dsa/qca/qca8k.h
|
|
@@ -416,5 +416,11 @@ struct qca8k_fdb {
|
|
|
|
/* Common setup function */
|
|
extern const struct qca8k_mib_desc ar8327_mib[];
|
|
+extern const struct regmap_access_table qca8k_readable_table;
|
|
+
|
|
+/* Common read/write/rmw function */
|
|
+int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
|
|
+int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
|
|
+int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
|
|
|
|
#endif /* __QCA8K_H */
|