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e2cea0506a
Add support for the FriendlyARM NanoPi R5C. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
270 lines
7.0 KiB
Diff
270 lines
7.0 KiB
Diff
From 41538742491c46100f570680c02fbdd0d2b6b880 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Tue, 30 May 2023 15:00:33 +0800
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Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5C
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FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
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Specification:
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- Rockchip RK3568
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- 1/4GB LPDDR4X RAM
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- 8/32GB eMMC
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- SD card slot
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- M.2 Connector
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- 2x USB 3.0 Port
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- 2x 2500 Base-T (PCIe, r8125)
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- HDMI 2.0
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- MIPI DSI/CSI
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- USB Type C 5V
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The device tree is taken from kernel v6.4-rc1.
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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---
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 3 +
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arch/arm/dts/rk3568-nanopi-r5c.dts | 112 +++++++++++++++++++++
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board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
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configs/nanopi-r5c-rk3568_defconfig | 85 ++++++++++++++++
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5 files changed, 208 insertions(+)
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create mode 100644 arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3568-nanopi-r5c.dts
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create mode 100644 configs/nanopi-r5c-rk3568_defconfig
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3566-anbernic-rgxx3.dtb \
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rk3566-radxa-cm3-io.dtb \
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rk3568-evb.dtb \
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+ rk3568-nanopi-r5c.dtb \
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rk3568-nanopi-r5s.dtb \
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rk3568-rock-3a.dtb
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--- /dev/null
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+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
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@@ -0,0 +1,3 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+
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+#include "rk3568-nanopi-r5s-u-boot.dtsi"
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--- /dev/null
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+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
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@@ -0,0 +1,112 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
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+ * (http://www.friendlyelec.com)
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+ *
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+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
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+ */
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+
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+/dts-v1/;
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+#include "rk3568-nanopi-r5s.dtsi"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R5C";
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+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&reset_button_pin>;
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+
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+ button-reset {
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+ debounce-interval = <50>;
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+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
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+ label = "reset";
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+ linux,code = <KEY_RESTART>;
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+ };
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+ };
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+
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+ gpio-leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
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+
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+ led-lan {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_LAN;
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+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ power_led: led-power {
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+ color = <LED_COLOR_ID_RED>;
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+ function = LED_FUNCTION_POWER;
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+ linux,default-trigger = "heartbeat";
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+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-wan {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_WAN;
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+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-wlan {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_WLAN;
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+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+};
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+
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+&pcie2x1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie20_reset_pin>;
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+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+};
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+
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+&pcie3x1 {
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+ num-lanes = <1>;
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+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie>;
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+ status = "okay";
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+};
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+
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+&pcie3x2 {
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+ num-lanes = <1>;
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+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie>;
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ gpio-leds {
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+ lan_led_pin: lan-led-pin {
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+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ power_led_pin: power-led-pin {
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+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ wan_led_pin: wan-led-pin {
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+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ wlan_led_pin: wlan-led-pin {
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+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pcie {
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+ pcie20_reset_pin: pcie20-reset-pin {
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+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
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+ };
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+ };
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+
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+ rockchip-key {
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+ reset_button_pin: reset-button-pin {
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+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
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+ };
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+ };
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+};
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--- a/board/rockchip/evb_rk3568/MAINTAINERS
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+++ b/board/rockchip/evb_rk3568/MAINTAINERS
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@@ -7,6 +7,13 @@ F: configs/evb-rk3568_defconfig
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F: arch/arm/dts/rk3568-evb-boot.dtsi
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F: arch/arm/dts/rk3568-evb.dts
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+NANOPI-R5C
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+M: Tianling Shen <cnsztl@gmail.com>
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+S: Maintained
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+F: configs/nanopi-r5c-rk3568_defconfig
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+F: arch/arm/dts/rk3568-nanopi-r5c.dts
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+F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
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+
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NANOPI-R5S
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M: Tianling Shen <cnsztl@gmail.com>
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S: Maintained
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--- /dev/null
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+++ b/configs/nanopi-r5c-rk3568_defconfig
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@@ -0,0 +1,85 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_TEXT_BASE=0x00a00000
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+CONFIG_SPL_LIBCOMMON_SUPPORT=y
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+CONFIG_SPL_LIBGENERIC_SUPPORT=y
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+CONFIG_NR_DRAM_BANKS=2
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+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
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+CONFIG_ROCKCHIP_RK3568=y
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+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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+CONFIG_SPL_SERIAL=y
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+CONFIG_SPL_STACK_R_ADDR=0x600000
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+CONFIG_TARGET_EVB_RK3568=y
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+CONFIG_SPL_STACK=0x400000
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+CONFIG_DEBUG_UART_BASE=0xFE660000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_SYS_LOAD_ADDR=0xc00800
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+CONFIG_DEBUG_UART=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_SPL_MAX_SIZE=0x40000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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+CONFIG_SPL_BSS_START_ADDR=0x4000000
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+CONFIG_SPL_BSS_MAX_SIZE=0x4000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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+CONFIG_SPL_STACK_R=y
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+CONFIG_SPL_ATF=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_I2C=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_PMIC=y
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+CONFIG_CMD_REGULATOR=y
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+# CONFIG_SPL_DOS_PARTITION is not set
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_OF_LIVE=y
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+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_SPL_DM_WARN=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_SPL_CLK=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MISC=y
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+CONFIG_SUPPORT_EMMC_RPMB=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_MMC_SDHCI=y
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+CONFIG_MMC_SDHCI_SDMA=y
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+CONFIG_MMC_SDHCI_ROCKCHIP=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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+CONFIG_POWER_DOMAIN=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_SPL_RAM=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYS_NS16550_MEM32=y
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+CONFIG_SYSRESET=y
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+CONFIG_SYSRESET_PSCI=y
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_XHCI_DWC3=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_DWC3=y
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+CONFIG_ERRNO_STR=y
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