mirror of
https://github.com/openwrt/openwrt.git
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5d51079fd0
This commit adds headers to the patches, so they can be applied with the git am command. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
400 lines
12 KiB
Diff
400 lines
12 KiB
Diff
From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001
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From: Eddi De Pieri <eddi@depieri.net>
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Date: Tue, 14 Oct 2014 11:04:00 +0000
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Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of
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Signed-off-by: Eddi De Pieri <eddi@depieri.net>
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---
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arch/mips/pci/Makefile | 2 +-
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arch/mips/pci/ifxmips_pcie.c | 151 +++++++++++++++++++++++++++----
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arch/mips/pci/ifxmips_pcie_vr9.h | 105 ---------------------
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3 files changed, 133 insertions(+), 125 deletions(-)
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
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obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
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obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
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obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
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-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
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+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o
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obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o
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obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
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obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
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--- a/arch/mips/pci/ifxmips_pcie.c
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+++ b/arch/mips/pci/ifxmips_pcie.c
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@@ -16,8 +16,15 @@
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#include <asm/paccess.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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+#include <linux/phy/phy.h>
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+#include <linux/regmap.h>
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+#include <linux/reset.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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+#include <linux/of_gpio.h>
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+#include <linux/of_platform.h>
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+
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#include "ifxmips_pcie.h"
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#include "ifxmips_pcie_reg.h"
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@@ -40,6 +47,10 @@
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static DEFINE_SPINLOCK(ifx_pcie_lock);
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u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
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+static int pcie_reset_gpio;
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+static struct phy *ltq_pcie_phy;
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+static struct reset_control *ltq_pcie_reset;
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+static struct regmap *ltq_rcu_regmap;
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static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
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{
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@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...
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printk("%s", buf);
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}
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+static inline void pcie_ep_gpio_rst_init(int pcie_port)
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+{
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+ gpio_direction_output(pcie_reset_gpio, 1);
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+ gpio_set_value(pcie_reset_gpio, 1);
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+}
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+
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+static inline void pcie_device_rst_assert(int pcie_port)
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+{
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+ gpio_set_value(pcie_reset_gpio, 0);
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+}
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+
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+static inline void pcie_device_rst_deassert(int pcie_port)
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+{
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+ mdelay(100);
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+ gpio_direction_output(pcie_reset_gpio, 1);
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+}
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static inline int pcie_ltssm_enable(int pcie_port)
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{
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@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct
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static int
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pcie_rc_initialize(int pcie_port)
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{
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- int i;
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+ int i, ret;
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#define IFX_PCIE_PHY_LOOP_CNT 5
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- pcie_rcu_endian_setup(pcie_port);
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,
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+ IFX_RCU_AHB_BE_PCIE_M);
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+
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+#ifdef CONFIG_IFX_PCIE_HW_SWAP
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
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+ IFX_RCU_AHB_BE_PCIE_S);
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+#else
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
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+ 0x0);
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+#endif
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+
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+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,
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+ 0x0);
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pcie_ep_gpio_rst_init(pcie_port);
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@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)
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* reset PCIe PHY will solve this issue
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*/
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for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
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- /* Disable PCIe PHY Analog part for sanity check */
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- pcie_phy_pmu_disable(pcie_port);
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-
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- pcie_phy_rst_assert(pcie_port);
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- pcie_phy_rst_deassert(pcie_port);
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-
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- /* Make sure PHY PLL is stable */
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- udelay(20);
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-
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- /* PCIe Core reset enabled, low active, sw programmed */
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- pcie_core_rst_assert(pcie_port);
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+ ret = phy_init(ltq_pcie_phy);
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+ if (ret)
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+ continue;
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/* Put PCIe EP in reset status */
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pcie_device_rst_assert(pcie_port);
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- /* PCI PHY & Core reset disabled, high active, sw programmed */
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- pcie_core_rst_deassert(pcie_port);
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+ udelay(1);
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+ reset_control_deassert(ltq_pcie_reset);
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- /* Already in a quiet state, program PLL, enable PHY, check ready bit */
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- pcie_phy_clock_mode_setup(pcie_port);
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+ ret = phy_power_on(ltq_pcie_phy);
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+ if (ret) {
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+ phy_exit(ltq_pcie_phy);
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+ continue;
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+ }
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/* Enable PCIe PHY and Clock */
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pcie_core_pmu_setup(pcie_port);
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@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)
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/* Once link is up, break out */
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if (pcie_app_loigc_setup(pcie_port) == 0)
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break;
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+
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+ phy_power_off(ltq_pcie_phy);
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+ reset_control_assert(ltq_pcie_reset);
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+ phy_exit(ltq_pcie_phy);
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}
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if (i >= IFX_PCIE_PHY_LOOP_CNT) {
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printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
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@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)
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return 0;
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}
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-static int __init ifx_pcie_bios_init(void)
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+static int ifx_pcie_bios_probe(struct platform_device *pdev)
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{
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+ struct device_node *node = pdev->dev.of_node;
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void __iomem *io_map_base;
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int pcie_port;
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int startup_port;
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+ struct device_node *np;
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+ struct pci_bus *bus;
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+
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+ /*
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+ * In case a PCI device is physical present, the Lantiq PCI driver need
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+ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
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+ * will work.
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+ *
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+ * In case the lantiq PCI driver is enabled in the device tree, check if
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+ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
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+ * registered.
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+ *
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+ * It will fail if there is another PCI controller, this controller is
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+ * registered before the Lantiq PCIe driver is probe and the lantiq PCI
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+ */
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+ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
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+
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+ if (of_device_is_available(np)) {
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+ bus = pci_find_next_bus(bus);
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+
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+ if (!bus)
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+ return -EPROBE_DEFER;
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+ }
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/* Enable AHB Master/ Slave */
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pcie_ahb_pmu_setup();
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startup_port = IFX_PCIE_PORT0;
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-
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+
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+ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
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+ if (IS_ERR(ltq_pcie_phy)) {
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+ dev_err(&pdev->dev, "failed to get the PCIe PHY\n");
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+ return PTR_ERR(ltq_pcie_phy);
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+ }
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+
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+ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
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+ if (IS_ERR(ltq_pcie_reset)) {
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+ dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
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+ return PTR_ERR(ltq_pcie_reset);
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+ }
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+
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+ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
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+ if (IS_ERR(ltq_rcu_regmap))
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+ return PTR_ERR(ltq_rcu_regmap);
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+
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+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
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+ if (gpio_is_valid(pcie_reset_gpio)) {
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+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
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+ if (ret) {
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+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
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+ return ret;
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+ }
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+ gpio_direction_output(pcie_reset_gpio, 1);
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+ }
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+
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for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
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if (pcie_rc_initialize(pcie_port) == 0) {
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IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
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@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi
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return -ENOMEM;
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}
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ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
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+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
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register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
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/* XXX, clear error status */
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@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi
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return 0;
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}
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+
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+static const struct of_device_id ifxmips_pcie_match[] = {
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+ { .compatible = "lantiq,pcie-xrx200" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
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+
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+static struct platform_driver ltq_pci_driver = {
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+ .probe = ifx_pcie_bios_probe,
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+ .driver = {
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+ .name = "pcie-xrx200",
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+ .owner = THIS_MODULE,
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+ .of_match_table = ifxmips_pcie_match,
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+ },
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+};
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+
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+int __init ifx_pcie_bios_init(void)
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+{
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+ int ret = platform_driver_register(<q_pci_driver);
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+ if (ret)
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+ pr_info("pcie-xrx200: Error registering platform driver!");
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+ return ret;
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+}
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+
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arch_initcall(ifx_pcie_bios_init);
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MODULE_LICENSE("GPL");
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--- a/arch/mips/pci/ifxmips_pcie_vr9.h
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+++ b/arch/mips/pci/ifxmips_pcie_vr9.h
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@@ -22,8 +22,6 @@
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#include <linux/gpio.h>
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#include <lantiq_soc.h>
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-#define IFX_PCIE_GPIO_RESET 494
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-
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#define IFX_REG_R32 ltq_r32
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#define IFX_REG_W32 ltq_w32
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#define CONFIG_IFX_PCIE_HW_SWAP
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@@ -53,21 +51,6 @@
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#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
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-static inline void pcie_ep_gpio_rst_init(int pcie_port)
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-{
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-
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- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
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- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
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- gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
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-
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-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
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-}
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-
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static inline void pcie_ahb_pmu_setup(void)
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{
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/* Enable AHB bus master/slave */
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@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo
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//AHBS_PMU_SETUP(IFX_PMU_ENABLE);
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}
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-static inline void pcie_rcu_endian_setup(int pcie_port)
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-{
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- u32 reg;
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-
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- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
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-#ifdef CONFIG_IFX_PCIE_HW_SWAP
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- reg |= IFX_RCU_AHB_BE_PCIE_M;
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- reg |= IFX_RCU_AHB_BE_PCIE_S;
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- reg &= ~IFX_RCU_AHB_BE_XBAR_M;
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-#else
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- reg |= IFX_RCU_AHB_BE_PCIE_M;
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- reg &= ~IFX_RCU_AHB_BE_PCIE_S;
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- reg &= ~IFX_RCU_AHB_BE_XBAR_M;
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-#endif /* CONFIG_IFX_PCIE_HW_SWAP */
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- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
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- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
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-}
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-
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static inline void pcie_phy_pmu_enable(int pcie_port)
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{
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struct clk *clk;
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@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable(
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// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
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}
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-static inline void pcie_pdi_big_endian(int pcie_port)
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-{
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- u32 reg;
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-
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- /* SRAM2PDI endianness control. */
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- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
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- /* Config AHB->PCIe and PDI endianness */
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- reg |= IFX_RCU_AHB_BE_PCIE_PDI;
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- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
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-}
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-
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static inline void pcie_pdi_pmu_enable(int pcie_port)
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{
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/* Enable PDI to access PCIe PHY register */
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@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i
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//PDI_PMU_SETUP(IFX_PMU_ENABLE);
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}
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-static inline void pcie_core_rst_assert(int pcie_port)
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-{
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- u32 reg;
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-
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- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
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-
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- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */
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- reg |= 0x00400000;
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- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
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-}
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-
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-static inline void pcie_core_rst_deassert(int pcie_port)
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-{
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- u32 reg;
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-
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- /* Make sure one micro-second delay */
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- udelay(1);
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-
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- /* Reset PCIe PHY & Core, bit 22 */
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- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
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- reg &= ~0x00400000;
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- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
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-}
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-
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-static inline void pcie_phy_rst_assert(int pcie_port)
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-{
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- u32 reg;
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-
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- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
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- reg |= 0x00001000; /* Bit 12 */
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- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
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-}
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-
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-static inline void pcie_phy_rst_deassert(int pcie_port)
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-{
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- u32 reg;
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-
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- /* Make sure one micro-second delay */
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- udelay(1);
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-
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- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
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- reg &= ~0x00001000; /* Bit 12 */
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- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
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-}
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-
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-static inline void pcie_device_rst_assert(int pcie_port)
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-{
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- gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
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-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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-}
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-
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-static inline void pcie_device_rst_deassert(int pcie_port)
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-{
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- mdelay(100);
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- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
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-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
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- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
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-}
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-
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static inline void pcie_core_pmu_setup(int pcie_port)
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{
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struct clk *clk;
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