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25afe99b31
the support is still WIP. next steps are to make the pmic and ethernet work. this is the first commit to make sure nothing gets lost. Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 47354
552 lines
14 KiB
Diff
552 lines
14 KiB
Diff
From a6bf117b5fe3acd76bbc45cc87fd80f589136e59 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Jun 2015 13:14:42 +0200
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Subject: [PATCH 66/76] arm: mediatek: add m7623 devicetree
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/mt7623-evb.dts | 162 ++++++++++++++++++
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arch/arm/boot/dts/mt7623.dtsi | 348 ++++++++++++++++++++++++++++++++++++++
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3 files changed, 511 insertions(+)
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create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
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create mode 100644 arch/arm/boot/dts/mt7623.dtsi
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 992736b..525392e 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -658,6 +658,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt6589-aquaris5.dtb \
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mt6592-evb.dtb \
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+ mt7623-evb.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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endif
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diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
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new file mode 100644
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index 0000000..759142f
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--- /dev/null
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+++ b/arch/arm/boot/dts/mt7623-evb.dts
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@@ -0,0 +1,162 @@
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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: Joe.C <yingjoe.chen@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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+#include "mt7623.dtsi"
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+
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+/ {
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+ model = "MediaTek MT7623 Evaluation Board";
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+ compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
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+
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+ chosen {
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+ stdout-path = &uart2;
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+ };
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+
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+ memory {
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+ reg = <0 0x80000000 0 0x10000000>;
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+ };
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+
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+ usb_p1_vbus: fixedregulator@0 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
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+ enable-active-high;
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+ };
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+};
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+
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+
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+&pio {
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+ pinctrl_uart2_default: uart2@0 {
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+ pins {
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+ pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
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+ <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
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+ };
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+ };
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+
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+ pinctrl_i2c0_default: i2c@0 {
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+ pins {
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+ pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
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+ <MT7623_PIN_76_SCL0_FUNC_SCL0>;
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+ };
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+ };
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+
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+ pinctrl_pcie_default: pcie@0 {
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+ pins {
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+ pinmux = <MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N>,
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+ <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
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+ <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>,
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+ <MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N>,
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+ <MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N>,
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+ <MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N>,
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+ <MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N>,
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+ <MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N>,
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+ <MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N>;
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+ };
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+ };
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+
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+ pinctrl_spi_default: spi@0 {
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+ pins {
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+ pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
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+ <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
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+ <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>,
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+ <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>;
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+ bias-disable;
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+ };
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+ };
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+};
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+
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+&thermal {
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ status = "okay";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart2_default>;
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c0_default>;
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+};
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+
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+&spi {
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+ status = "okay";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_spi_default>;
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+
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+ m25p80@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "mx25l12805d";
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+ reg = <0 0 0 0>;
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+ linux,modalias = "m25p80", "w25q128";
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+ spi-max-frequency = <10000000>;
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+
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+ partition@0 {
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+ label = "u-boot";
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+ reg = <0x0 0x30000>;
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+ read-only;
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+ };
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+
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+ partition@30000 {
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+ label = "u-boot-env";
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+ reg = <0x30000 0x10000>;
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+ read-only;
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+ };
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+
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+ factory: partition@40000 {
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+ label = "factory";
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+ reg = <0x40000 0x10000>;
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+ read-only;
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+ };
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+
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+ partition@50000 {
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+ label = "firmware";
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+ reg = <0x50000 0xfb0000>;
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+ };
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+ };
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+};
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+
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+&mmc0 {
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+ status = "okay";
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+
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+// pinctrl-names = "default", "state_uhs";
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+// pinctrl-0 = <&mmc0_pins_default>;
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+// pinctrl-1 = <&mmc0_pins_uhs>;
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+ bus-width = <8>;
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+ max-frequency = <50000000>;
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+ cap-mmc-highspeed;
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+// vmmc-supply = <&mt6397_vemc_3v3_reg>;
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+// vqmmc-supply = <&mt6397_vio18_reg>;
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+ non-removable;
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+};
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+
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+&u3phy {
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+ reg-p1-vbus-supply = <&usb_p1_vbus>;
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+};
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+
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+&pcie {
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+ status = "okay";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pcie_default>;
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+};
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diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
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new file mode 100644
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index 0000000..ba74ed9
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--- /dev/null
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -0,0 +1,348 @@
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+/*
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+ * Copyright (c) 2014 MediaTek Inc.
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+ * Author: Joe.C <yingjoe.chen@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <dt-bindings/clock/mt7623-clk.h>
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
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+#include <dt-bindings/reset-controller/mt7623-resets.h>
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+#include "skeleton64.dtsi"
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+
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+/ {
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+ compatible = "mediatek,mt7623";
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+ interrupt-parent = <&sysirq>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ enable-method = "mediatek,mt65xx-smp";
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+ cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x0>;
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+ };
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+ cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x1>;
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+ };
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+ cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x2>;
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+ };
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+ cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x3>;
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+ };
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+
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+ };
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+
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+ clk26m: oscillator@0 {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <26000000>;
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+ clock-output-names = "clk26m";
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+ };
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+
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+ clk32k: oscillator@1 {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <32000>;
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+ clock-output-names = "clk32k";
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+ };
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+
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>;
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+ clock-frequency = <13000000>;
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+ arm,cpu-registers-not-fw-configured;
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+ };
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+
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+ thermal-zones {
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+ cpu_thermal: cpu_thermal {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <5000>;
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+
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+ thermal-sensors = <&thermal 1>;
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+ };
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+ };
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+
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ compatible = "simple-bus";
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+ ranges;
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+
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+ topckgen: topckgen@10000000 {
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+ compatible = "mediatek,mt7623-topckgen";
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+ reg = <0 0x10000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ infracfg: infracfg@10001000 {
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+ compatible = "mediatek,mt7623-infracfg", "syscon";
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+ reg = <0 0x10001000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pericfg: pericfg@10003000 {
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+ compatible = "mediatek,mt7623-pericfg", "syscon";
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+ reg = <0 0x10003000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ /*
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+ * Pinctrl access register at 0x10005000 through regmap.
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+ * Register 0x1000b000 is used by EINT.
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+ */
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+ pio: pinctrl@10005000 {
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+ compatible = "mediatek,mt7623-pinctrl";
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+ reg = <0 0x1000b000 0 0x1000>;
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+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
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+ pins-are-numbered;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ syscfg_pctl_a: syscfg_pctl_a@10005000 {
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+ compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
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+ reg = <0 0x10005000 0 0x1000>;
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+ };
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+
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+ wdt: watchdog@10007000 {
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+ compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt";
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+ reg = <0 0x10007000 0 0x18>;
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+ };
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+
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+ timer: timer@10008000 {
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+ compatible = "mediatek,mt7623-timer",
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+ "mediatek,mt6577-timer";
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+ reg = <0 0x10008000 0 0x80>;
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_AXI_SEL>,
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+ <&topckgen CLK_TOP_RTC_SEL>;
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+ clock-names = "system-clk", "rtc-clk";
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+ };
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+
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+ sysirq: interrupt-controller@10200100 {
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+ compatible = "mediatek,mt7623-sysirq",
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+ "mediatek,mt6577-sysirq";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ reg = <0 0x10200100 0 0x1c>;
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+ };
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+
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+ apmixedsys: apmixedsys@10209000 {
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+ compatible = "mediatek,mt7623-apmixedsys";
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+ reg = <0 0x10209000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ gic: interrupt-controller@10211000 {
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+ compatible = "arm,cortex-a7-gic";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ reg = <0 0x10211000 0 0x1000>,
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+ <0 0x10212000 0 0x1000>,
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+ <0 0x10214000 0 0x2000>,
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+ <0 0x10216000 0 0x2000>;
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+ };
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+
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+ auxadc: auxadc@11001000 {
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+ compatible = "mediatek,mt7623-auxadc", "mediatek,mt8173-auxadc";
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+ reg = <0 0x11001000 0 0x1000>;
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+ };
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+
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+ uart0: serial@11006000 {
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+ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
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+ reg = <0 0x11002000 0 0x400>;
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+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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+ clock-names = "baud", "bus";
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+
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+ status = "disabled";
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+ };
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+
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+ uart1: serial@11007000 {
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+ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
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+ reg = <0 0x11003000 0 0x400>;
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+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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+ clock-names = "baud", "bus";
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+
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+ status = "disabled";
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+ };
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+
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+ uart2: serial@11008000 {
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+ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
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+ reg = <0 0x11004000 0 0x400>;
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+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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+ clock-names = "baud", "bus";
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+
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+ status = "disabled";
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+ };
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+
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+ uart3: serial@11009000 {
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+ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
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+ reg = <0 0x11005000 0 0x400>;
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+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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+ clock-names = "baud", "bus";
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+
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+ status = "disabled";
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+ };
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+
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+ spi: spi@1100a000 {
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+ compatible = "medi/THEatek,mt7623-spi", "mediatek,mt6589-spi";
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+ reg = <0 0x1100a000 0 0x1000>;
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+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_SPI0>;
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+ clock-names = "main";
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+
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+ status = "disabled";
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+ };
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+
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+ thermal: thermal@1100b000 {
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+ #thermal-sensor-cells = <1>;
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+ compatible = "mediatek,mt7623-thermal", "mediatek,mt8173-thermal";
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+ reg = <0 0x1100b000 0 0x1000>;
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+ interrupts = <0 38 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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+ clock-names = "therm", "auxadc";
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+ resets = <&pericfg MT7623_PERI_THERM_SW_RST>;
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+ reset-names = "therm";
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+ auxadc = <&auxadc>;
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+ apmixedsys = <&apmixedsys>;
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+
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+ status = "disabled";
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+ };
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+
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+ i2c0: i2c@11007000 {
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+ compatible = "mediatek,mt7623-i2c", "mediatek,mt6577-i2c";
|
|
+ reg = <0 0x11007000 0 0x70>,
|
|
+ <0 0x11000300 0 0x80>;
|
|
+ interrupts = <0 44 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clock-frequency = <400000>;
|
|
+ clock-div = <16>;
|
|
+ clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
|
|
+ clock-names = "main", "dma";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@11230000 {
|
|
+ compatible = "mediatek,mt7623-mmc",
|
|
+ "mediatek,mt8135-mmc";
|
|
+ reg = <0 0x11230000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_MSDC20_1>,
|
|
+ <&topckgen CLK_TOP_MSDC30_0_SEL>;
|
|
+ clock-names = "source", "hclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb: usb30@11270000 {
|
|
+ compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci", "generic-xhci";
|
|
+ reg = <0 0x11270000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
|
|
+ usb-phy = <&u3phy>;
|
|
+ usb3-lpm-capable;
|
|
+ };
|
|
+
|
|
+ u3phy: usb-phy@11271000 {
|
|
+ compatible = "mediatek,mt7623-u3phy", "mediatek,mt8173-u3phy";
|
|
+ reg = <0 0x11271000 0 0x3000>,
|
|
+ <0 0x11280000 0 0x20000>;
|
|
+// power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
|
|
+// reg-vusb33-supply = <&mt6397_vusb_reg>;
|
|
+ clocks = <&pericfg CLK_PERI_USB0>,
|
|
+ <&pericfg CLK_PERI_USB1>,
|
|
+ <&topckgen CLK_TOP_USB20_SEL>;
|
|
+// <&apmixedsys CLK_APMIXED_REF2USB_TX>;
|
|
+ clock-names = "wakeup_deb_p0",
|
|
+ "wakeup_deb_p1",
|
|
+ "sys_mac";
|
|
+// "u3phya_ref";
|
|
+ disable-usb2-p1;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethernet@1B100000 {
|
|
+ compatible = "mediatek,mt7623-net";
|
|
+ interrupts = <0 200 IRQ_TYPE_LEVEL_LOW>;
|
|
+ };
|
|
+
|
|
+ pcie: pcie@1a140000 {
|
|
+ compatible = "mediatek,mt7623-pcie";
|
|
+ reg = <0 0x1a140000 0 0x10000>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ device_type = "pci";
|
|
+
|
|
+ bus-range = <0 255>;
|
|
+ ranges = <
|
|
+ 0x02000000 0 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
|
|
+ 0x01000000 0 0 0x00000000 0x1A160000 0 0x00010000 /* io space */
|
|
+ >;
|
|
+
|
|
+ pcie0 {
|
|
+ reg = <0x0000 0 0 0 0>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ device_type = "pci";
|
|
+ };
|
|
+
|
|
+ pcie1 {
|
|
+ reg = <0x0800 0 0 0 0>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ device_type = "pci";
|
|
+ };
|
|
+
|
|
+ pcie2 {
|
|
+ reg = <0x1000 0 0 0 0>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ device_type = "pci";
|
|
+ };
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+};
|
|
--
|
|
1.7.10.4
|
|
|