openwrt/target/linux/bcm27xx/patches-5.15/950-0606-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch
Rui Salvaterra 251a382c28 kernel: bump 5.15 to 5.15.46
Deleted (upstreamed):
generic/backport-5.15/400-mtdblock-warn-if-opened-on-NAND.patch [01]
generic/backport-5.15/420-v5.19-01-mtd-spinand-gigadevice-fix-Quad-IO-for-GD5F1GQ5UExxG.patch [02]
bcm27xx/patches-5.15/950-0029-Revert-mailbox-avoid-timer-start-from-callback.patch [03]
bcm27xx/patches-5.15/950-0417-bcm2711_thermal-Don-t-clamp-temperature-at-zero.patch [04]
bcm27xx/patches-5.15/950-0740-drm-vc4-hvs-Fix-frame-count-register-readout.patch [05]
bcm27xx/patches-5.15/950-0755-drm-vc4-hvs-Reset-muxes-at-probe-time.patch [06]
bcm27xx/patches-5.15/950-0759-drm-vc4-txp-Don-t-set-TXP_VSTART_AT_EOF.patch [07]
bcm27xx/patches-5.15/950-0760-drm-vc4-txp-Force-alpha-to-be-0xff-if-it-s-disabled.patch [08]
bcm53xx/patches-5.15/031-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch [09]
mediatek/patches-5.15/102-mt7629-enable-arch-timer.patch [10]

Manually rebased:
bcm27xx/patches-5.15/950-0741-drm-vc4-hvs-Use-pointer-to-HVS-in-HVS_READ-and-HVS_W.patch

[01] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=f41c9418c5898c01634675150696da290fb86796
[02] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=d5b66645305c6f3a1b2cf75cee4157b07f293309
[03] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=119f99209d8531359bcb935f252ec435f9d21b13
[04] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=c4e1280abead1552e1764684079a43e222ccd163
[05] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=08465a1889cb48ec64431e9db745b5be15399251
[06] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=0e26a6da02e63b75b629573d13966c36aa6264f0
[07] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=01c9020b2e7c85e394879f34851805179ac3d1d8
[08] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=d47f85cc0171a5d3c5bd8cbb8a98983ca3357cbd
[09] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=5151f24ac937ff7eb1f078257c66e3c0f0296010
[10] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.46&id=ffea838686b82fbb2801cdfad6ba5309d15c032d

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
2022-06-27 00:57:16 +02:00

74 lines
2.9 KiB
Diff

From a1d5ce866f2e2062246343af757c22e9abe4e844 Mon Sep 17 00:00:00 2001
From: Jonathan Bell <jonathan@raspberrypi.com>
Date: Mon, 13 Dec 2021 16:04:03 +0000
Subject: [PATCH] usb: xhci: add VLI_TRB_CACHE_BUG quirk
The VL805 fetches up to 4 transfer TRBs at a time. TRB reads don't cross
a 64B boundary, and if a TRB is fetched and is not on a 64B boundary,
the read is sized up to the next 64B boundary.
However the VL805 implements a readahead prefetch for TRBs on a transfer
ring. This fetches the next 64B after any TRB read has happened. Near
the end of a ring segment, the prefetcher can read the first 64B of the
next page in physical memory and this is where the behaviour causes a
bug.
The controller does not tag reads with which endpoint they are for, so
if the start of the next page is a ring segment used by a victim
endpoint, and the victim endpoint is about to fetch TRBs from the start
of the segment, the victim endpoint will read from the prefetched data
and not perform a read to main memory. If the data is stale, the ring
cycle state bit may not be correct and the endpoint will silently halt.
Adjust trbs_per_seg for transfer rings allocated for this controller.
See https://github.com/raspberrypi/linux/issues/4685
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
---
drivers/usb/host/xhci-mem.c | 11 +++++++++++
drivers/usb/host/xhci-pci.c | 1 +
drivers/usb/host/xhci.h | 1 +
3 files changed, 13 insertions(+)
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -392,6 +392,17 @@ struct xhci_ring *xhci_ring_alloc(struct
return ring;
ring->trbs_per_seg = TRBS_PER_SEGMENT;
+ /*
+ * The Via VL805 has a bug where cache readahead will fetch off the end
+ * of a page if the Link TRB of a transfer ring is in the last 4 slots.
+ * Where there are consecutive physical pages containing ring segments,
+ * this can cause a desync between the controller's view of a ring
+ * and the host.
+ */
+ if (xhci->quirks & XHCI_VLI_TRB_CACHE_BUG &&
+ type != TYPE_EVENT && type != TYPE_COMMAND)
+ ring->trbs_per_seg -= 4;
+
ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
&ring->last_seg, num_segs, ring->trbs_per_seg,
cycle_state, type, max_packet, flags);
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -301,6 +301,7 @@ static void xhci_pci_quirks(struct devic
xhci->quirks |= XHCI_LPM_SUPPORT;
xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
+ xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
}
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1905,6 +1905,7 @@ struct xhci_hcd {
#define XHCI_BROKEN_D3COLD BIT_ULL(41)
#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(43)
+#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(44)
unsigned int num_active_eps;
unsigned int limit_active_eps;