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2464a9a8a4
Refreshed all patches. Compile-tested on: x86_64, ath79, lantiq Runtime-tested on: x86_64, ath79 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
66 lines
2.7 KiB
Diff
66 lines
2.7 KiB
Diff
From 094a648bc2217a9624f35224059c3eac86196143 Mon Sep 17 00:00:00 2001
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From: Joakim Zhang <qiangqing.zhang@nxp.com>
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Date: Fri, 12 Jul 2019 08:02:51 +0000
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Subject: [PATCH] can: flexcan: add ISO CAN FD feature support
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ISO CAN FD is introduced to increase the failture detection capability
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than non-ISO CAN FD. The non-ISO CAN FD is still supported by FlexCAN so
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that it can be used mainly during an intermediate phase, for evaluation
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and development purposes.
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Therefore, it is strongly recommended to configure FlexCAN to the ISO
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CAN FD protocol by setting the ISOCANFDEN field in the CTRL2 register.
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NOTE: If you only set "fd on", driver will use ISO FD mode by default.
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You should set "fd-non-iso on" after setting "fd on" if you want to use
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NON ISO FD mode.
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Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 8 +++++++-
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1 file changed, 7 insertions(+), 1 deletion(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -92,6 +92,7 @@
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#define FLEXCAN_CTRL2_MRP BIT(18)
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#define FLEXCAN_CTRL2_RRS BIT(17)
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#define FLEXCAN_CTRL2_EACEN BIT(16)
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+#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
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/* FLEXCAN memory error control register (MECR) bits */
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#define FLEXCAN_MECR_ECRWRDIS BIT(31)
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@@ -1326,6 +1327,7 @@ static int flexcan_chip_start(struct net
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reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
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reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3));
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reg_mcr = priv->read(®s->mcr) & ~FLEXCAN_MCR_FDEN;
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+ reg_ctrl2 = priv->read(®s->ctrl2) & ~FLEXCAN_CTRL2_ISOCANFDEN;
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/* support BRS when set CAN FD mode
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* 64 bytes payload per MB and 7 MBs per RAM block by default
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@@ -1335,10 +1337,14 @@ static int flexcan_chip_start(struct net
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reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
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reg_fdctrl |= FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3);
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reg_mcr |= FLEXCAN_MCR_FDEN;
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+
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+ if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
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+ reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
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}
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priv->write(reg_fdctrl, ®s->fdctrl);
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priv->write(reg_mcr, ®s->mcr);
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+ priv->write(reg_ctrl2, ®s->ctrl2);
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}
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if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
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@@ -1862,7 +1868,7 @@ static int flexcan_probe(struct platform
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
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- priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
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+ priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO;
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priv->can.bittiming_const = &flexcan_fd_bittiming_const;
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priv->can.data_bittiming_const = &flexcan_fd_data_bittiming_const;
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} else {
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