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20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
From 06c340cc854b1c8c275968c2830fbe8a5c3b0e4e Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 18 Jun 2021 21:52:28 +0100
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Subject: [PATCH] drm/vc4: Correct DSI divider calculations
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The divider calculations tried to find the divider
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just faster than the clock requested. However if
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it required a divider of 7 then the for loop
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aborted without handling the "error" case, and could
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end up with a clock lower than requested.
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Correct the loop so that we always have a clock greater
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than requested.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 6 ++----
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1 file changed, 2 insertions(+), 4 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -850,11 +850,9 @@ static bool vc4_dsi_encoder_mode_fixup(s
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/* Find what divider gets us a faster clock than the requested
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* pixel clock.
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*/
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- for (divider = 1; divider < 8; divider++) {
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- if (parent_rate / divider < pll_clock) {
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- divider--;
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+ for (divider = 1; divider < 7; divider++) {
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+ if (parent_rate / (divider + 1) < pll_clock)
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break;
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- }
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}
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/* Now that we've picked a PLL divider, calculate back to its
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