mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
f07e572f64
bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From cfe0832e8306cd9955f682b7314a5a6fc3b9d514 Mon Sep 17 00:00:00 2001
|
|
From: Eric Anholt <eric@anholt.net>
|
|
Date: Thu, 2 May 2019 15:11:05 -0700
|
|
Subject: [PATCH] clk: bcm2835: Add support for setting leaf clock
|
|
rates while running.
|
|
|
|
As long as you wait for !BUSY, you can do glitch-free updates of clock
|
|
rate while the clock is running.
|
|
|
|
Signed-off-by: Eric Anholt <eric@anholt.net>
|
|
---
|
|
drivers/clk/bcm/clk-bcm2835.c | 22 +++++++++++++---------
|
|
1 file changed, 13 insertions(+), 9 deletions(-)
|
|
|
|
--- a/drivers/clk/bcm/clk-bcm2835.c
|
|
+++ b/drivers/clk/bcm/clk-bcm2835.c
|
|
@@ -1114,15 +1114,19 @@ static int bcm2835_clock_set_rate(struct
|
|
|
|
spin_lock(&cprman->regs_lock);
|
|
|
|
- /*
|
|
- * Setting up frac support
|
|
- *
|
|
- * In principle it is recommended to stop/start the clock first,
|
|
- * but as we set CLK_SET_RATE_GATE during registration of the
|
|
- * clock this requirement should be take care of by the
|
|
- * clk-framework.
|
|
+ ctl = cprman_read(cprman, data->ctl_reg);
|
|
+
|
|
+ /* If the clock is running, we have to pause clock generation while
|
|
+ * updating the control and div regs. This is glitchless (no clock
|
|
+ * signals generated faster than the rate) but each reg access is two
|
|
+ * OSC cycles so the clock will slow down for a moment.
|
|
*/
|
|
- ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
|
|
+ if (ctl & CM_ENABLE) {
|
|
+ cprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE);
|
|
+ bcm2835_clock_wait_busy(clock);
|
|
+ }
|
|
+
|
|
+ ctl &= ~CM_FRAC;
|
|
ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
|
|
cprman_write(cprman, data->ctl_reg, ctl);
|
|
|
|
@@ -1494,7 +1498,7 @@ static struct clk_hw *bcm2835_register_c
|
|
init.ops = &bcm2835_vpu_clock_clk_ops;
|
|
} else {
|
|
init.ops = &bcm2835_clock_clk_ops;
|
|
- init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
|
+ init.flags |= CLK_SET_PARENT_GATE;
|
|
|
|
/* If the clock wasn't actually enabled at boot, it's not
|
|
* critical.
|