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e39414ed07
Refreshed all patches Dropped upstreamed patches: 522-PCI-aardvark-fix-logic-in-PCI-configuration-read-write-functions.patch 523-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_rd_conf.patch 525-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-legacy-irq-mode.patch 527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch updated patches: 524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch 030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch Added new ARM64 symbol: CONFIG_ARM64_ERRATUM_1024718 Compile-tested on: cns3xxx, imx6, mvebu (arm64), x86_64 Runtime-tested on: cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
131 lines
3.6 KiB
Diff
131 lines
3.6 KiB
Diff
From cb376159800b9b44be76949c3aee89eb06d29faa Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 6 Mar 2018 09:55:13 +0100
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Subject: [PATCH 07/27] irqchip/irq-ath79-intc: add irq cascade driver for
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QCA9556 SoCs
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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drivers/irqchip/Makefile | 1 +
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drivers/irqchip/irq-ath79-intc.c | 104 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 105 insertions(+)
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create mode 100644 drivers/irqchip/irq-ath79-intc.c
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--- a/drivers/irqchip/Makefile
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+++ b/drivers/irqchip/Makefile
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@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
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obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
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+obj-$(CONFIG_ATH79) += irq-ath79-intc.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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--- /dev/null
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+++ b/drivers/irqchip/irq-ath79-intc.c
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@@ -0,0 +1,104 @@
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+/*
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+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling
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+ *
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+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/interrupt.h>
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+#include <linux/irqchip.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/irqdomain.h>
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+
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+#include <asm/irq_cpu.h>
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+#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+
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+#define ATH79_MAX_INTC_CASCADE 3
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+
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+struct ath79_intc {
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+ struct irq_chip chip;
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+ u32 irq;
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+ u32 pending_mask;
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+ u32 irq_mask[ATH79_MAX_INTC_CASCADE];
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+};
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+
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+static void ath79_intc_irq_handler(struct irq_desc *desc)
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+{
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+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
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+ struct ath79_intc *intc = domain->host_data;
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+ u32 pending;
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+
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+ pending = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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+ pending &= intc->pending_mask;
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+
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+ if (pending) {
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+ int i;
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+
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+ for (i = 0; i < domain->hwirq_max; i++)
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+ if (pending & intc->irq_mask[i])
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+ generic_handle_irq(irq_find_mapping(domain, i));
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+ } else {
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+ spurious_interrupt();
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+ }
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+}
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+
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+static void ath79_intc_irq_unmask(struct irq_data *d)
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+{
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+}
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+
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+static void ath79_intc_irq_mask(struct irq_data *d)
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+{
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+}
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+
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+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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+{
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+ struct ath79_intc *intc = d->host_data;
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+
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+ irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops ath79_irq_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = ath79_intc_map,
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+};
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+
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+static int __init qca9556_intc_of_init(
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+ struct device_node *node, struct device_node *parent)
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+{
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+ struct irq_domain *domain;
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+ struct ath79_intc *intc;
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+ int cnt, i;
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+
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+ cnt = of_property_count_u32_elems(node, "qcom,pending-bits");
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+ if (cnt > ATH79_MAX_INTC_CASCADE)
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+ panic("Too many INTC pending bits\n");
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+
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+ intc = kzalloc(sizeof(*intc), GFP_KERNEL);
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+ if (!intc)
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+ panic("Failed to allocate INTC memory\n");
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+ intc->chip.name = "INTC";
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+ intc->chip.irq_unmask = ath79_intc_irq_unmask,
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+ intc->chip.irq_mask = ath79_intc_irq_mask,
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+
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+ of_property_read_u32_array(node, "qcom,pending-bits", intc->irq_mask, cnt);
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+ for (i = 0; i < cnt; i++)
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+ intc->pending_mask |= intc->irq_mask[i];
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+
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+ intc->irq = irq_of_parse_and_map(node, 0);
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+ if (!intc->irq)
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+ panic("Failed to get INTC IRQ");
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+
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+ domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
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+ irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
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+
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+ return 0;
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+}
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+IRQCHIP_DECLARE(qca9556_intc, "qcom,qca9556-intc",
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+ qca9556_intc_of_init);
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