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b9d58f7e06
generic: Add/rename patches for upstream consistency
ipq40xx: generic-level patch replaces same-source patches-4.19/
082-v4.20-mtd-spinand-winbond-Add-support-for-W25N01GV.patch
The SPI-NAND framework from Linux uses common driver code that is then
"tuned" by a tiny struct of chip-specific data that describes
available commands, timing, and layout (data and OOB data). Several
manufacturers and chips have been added since 4.19, several of which
are used in devices already supported by OpenWrt (typically with no or
"legacy" access to their NAND memory). This commit catches up the
supported-chip definitions through Linux 5.2-rc6 and linux/next.
The driver is only compiled for platforms with CONFIG_MTD_SPI_NAND=y.
This presently includes ipq40xx and pistachio, with the addition of
ath79-nand in these commits (and not ath79-generic or ath79-tiny).
Upstream patches refreshed against 4.19.75
Build-tested-on: ipq40xx
Run-tested-on: ath79-nand
Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
130 lines
3.6 KiB
Diff
130 lines
3.6 KiB
Diff
From c40c7a990a46e5102a1cc4190557bf315d32d80d Mon Sep 17 00:00:00 2001
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From: Stefan Roese <sr@denx.de>
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Date: Thu, 24 Jan 2019 13:48:06 +0100
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Subject: [PATCH 8/8] mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG
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Add support for GigaDevice GD5F1GQ4UExxG SPI NAND chip.
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Signed-off-by: Stefan Roese <sr@denx.de>
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Cc: Chuanhong Guo <gch981213@gmail.com>
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Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
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Cc: Miquel Raynal <miquel.raynal@bootlin.com>
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Cc: Boris Brezillon <bbrezillon@kernel.org>
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Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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---
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drivers/mtd/nand/spi/gigadevice.c | 83 +++++++++++++++++++++++++++++++
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1 file changed, 83 insertions(+)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -12,6 +12,8 @@
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#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
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#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
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+#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
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+
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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@@ -81,11 +83,83 @@ static int gd5fxgq4xa_ecc_get_status(str
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return -EINVAL;
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}
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+static int gd5fxgq4uexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ region->offset = 64;
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+ region->length = 64;
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+
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+ return 0;
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+}
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+
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+static int gd5fxgq4uexxg_ooblayout_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *region)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ /* Reserve 1 bytes for the BBM. */
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+ region->offset = 1;
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+ region->length = 63;
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+
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+ return 0;
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+}
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+
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+static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ u8 status2;
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+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
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+ &status2);
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+ int ret;
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+
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+ switch (status & STATUS_ECC_MASK) {
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+ case STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
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+ /*
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+ * Read status2 register to determine a more fine grained
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+ * bit error status
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+ */
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+ ret = spi_mem_exec_op(spinand->spimem, &op);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * 4 ... 7 bits are flipped (1..4 can't be detected, so
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+ * report the maximum of 4 in this case
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+ */
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+ /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
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+ return ((status & STATUS_ECC_MASK) >> 2) |
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+ ((status2 & STATUS_ECC_MASK) >> 4);
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+
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+ case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
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+ return 8;
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+
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+ case STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
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.ecc = gd5fxgq4xa_ooblayout_ecc,
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.free = gd5fxgq4xa_ooblayout_free,
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};
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+static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = {
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+ .ecc = gd5fxgq4uexxg_ooblayout_ecc,
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+ .free = gd5fxgq4uexxg_ooblayout_free,
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+};
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+
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static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO("GD5F1GQ4xA", 0xF1,
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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@@ -114,6 +188,15 @@ static const struct spinand_info gigadev
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0,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ 0,
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+ SPINAND_ECCINFO(&gd5fxgq4uexxg_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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};
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static int gigadevice_spinand_detect(struct spinand_device *spinand)
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