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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
201 lines
6.2 KiB
Diff
201 lines
6.2 KiB
Diff
From 201ce99897ff5fff2612cb633406e90c1b2acbcf Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Mon, 8 Jan 2024 19:05:59 +0800
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Subject: [PATCH 022/116] PCI: microchip: Move setup functions to
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pcie-plda-host.c
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Move setup functions to common pcie-plda-host.c. So these two functions
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can be re-used.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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---
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drivers/pci/controller/plda/Kconfig | 4 +
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drivers/pci/controller/plda/Makefile | 1 +
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.../pci/controller/plda/pcie-microchip-host.c | 59 ---------------
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drivers/pci/controller/plda/pcie-plda-host.c | 74 +++++++++++++++++++
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drivers/pci/controller/plda/pcie-plda.h | 5 ++
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5 files changed, 84 insertions(+), 59 deletions(-)
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create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c
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--- a/drivers/pci/controller/plda/Kconfig
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+++ b/drivers/pci/controller/plda/Kconfig
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@@ -3,10 +3,14 @@
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menu "PLDA-based PCIe controllers"
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depends on PCI
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+config PCIE_PLDA_HOST
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+ bool
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+
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config PCIE_MICROCHIP_HOST
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tristate "Microchip AXI PCIe controller"
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depends on PCI_MSI && OF
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select PCI_HOST_COMMON
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+ select PCIE_PLDA_HOST
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help
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Say Y here if you want kernel to support the Microchip AXI PCIe
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Host Bridge driver.
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--- a/drivers/pci/controller/plda/Makefile
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+++ b/drivers/pci/controller/plda/Makefile
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@@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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+obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o
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obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
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--- a/drivers/pci/controller/plda/pcie-microchip-host.c
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+++ b/drivers/pci/controller/plda/pcie-microchip-host.c
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@@ -838,65 +838,6 @@ static int mc_pcie_init_irq_domains(stru
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return mc_allocate_msi_domains(port);
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}
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-static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
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- phys_addr_t axi_addr, phys_addr_t pci_addr,
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- size_t size)
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-{
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- u32 atr_sz = ilog2(size) - 1;
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- u32 val;
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-
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- if (index == 0)
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- val = PCIE_CONFIG_INTERFACE;
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- else
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- val = PCIE_TX_RX_INTERFACE;
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-
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- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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- ATR0_AXI4_SLV0_TRSL_PARAM);
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-
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- val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |
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- ATR_IMPL_ENABLE;
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- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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- ATR0_AXI4_SLV0_SRCADDR_PARAM);
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-
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- val = upper_32_bits(axi_addr);
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- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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- ATR0_AXI4_SLV0_SRC_ADDR);
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-
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- val = lower_32_bits(pci_addr);
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- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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- ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
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-
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- val = upper_32_bits(pci_addr);
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- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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- ATR0_AXI4_SLV0_TRSL_ADDR_UDW);
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-
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- val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
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- val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
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- writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
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- writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
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-}
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-
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-static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge,
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- struct plda_pcie_rp *port)
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-{
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- void __iomem *bridge_base_addr = port->bridge_addr;
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- struct resource_entry *entry;
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- u64 pci_addr;
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- u32 index = 1;
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-
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- resource_list_for_each_entry(entry, &bridge->windows) {
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- if (resource_type(entry->res) == IORESOURCE_MEM) {
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- pci_addr = entry->res->start - entry->offset;
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- plda_pcie_setup_window(bridge_base_addr, index,
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- entry->res->start, pci_addr,
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- resource_size(entry->res));
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- index++;
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- }
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- }
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-
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- return 0;
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-}
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-
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static inline void mc_clear_secs(struct mc_pcie *port)
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{
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void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
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--- /dev/null
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+++ b/drivers/pci/controller/plda/pcie-plda-host.c
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@@ -0,0 +1,74 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * PLDA PCIe XpressRich host controller driver
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+ *
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+ * Copyright (C) 2023 Microchip Co. Ltd
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+ *
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+ * Author: Daire McNamara <daire.mcnamara@microchip.com>
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+ */
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+
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+#include <linux/pci_regs.h>
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+#include <linux/pci-ecam.h>
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+
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+#include "pcie-plda.h"
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+
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+void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
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+ phys_addr_t axi_addr, phys_addr_t pci_addr,
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+ size_t size)
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+{
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+ u32 atr_sz = ilog2(size) - 1;
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+ u32 val;
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+
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+ if (index == 0)
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+ val = PCIE_CONFIG_INTERFACE;
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+ else
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+ val = PCIE_TX_RX_INTERFACE;
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+
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+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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+ ATR0_AXI4_SLV0_TRSL_PARAM);
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+
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+ val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |
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+ ATR_IMPL_ENABLE;
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+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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+ ATR0_AXI4_SLV0_SRCADDR_PARAM);
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+
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+ val = upper_32_bits(axi_addr);
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+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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+ ATR0_AXI4_SLV0_SRC_ADDR);
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+
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+ val = lower_32_bits(pci_addr);
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+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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+ ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
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+
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+ val = upper_32_bits(pci_addr);
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+ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
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+ ATR0_AXI4_SLV0_TRSL_ADDR_UDW);
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+
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+ val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
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+ val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
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+ writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
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+ writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
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+}
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+EXPORT_SYMBOL_GPL(plda_pcie_setup_window);
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+
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+int plda_pcie_setup_iomems(struct pci_host_bridge *bridge,
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+ struct plda_pcie_rp *port)
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+{
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+ void __iomem *bridge_base_addr = port->bridge_addr;
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+ struct resource_entry *entry;
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+ u64 pci_addr;
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+ u32 index = 1;
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+
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+ resource_list_for_each_entry(entry, &bridge->windows) {
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+ if (resource_type(entry->res) == IORESOURCE_MEM) {
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+ pci_addr = entry->res->start - entry->offset;
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+ plda_pcie_setup_window(bridge_base_addr, index,
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+ entry->res->start, pci_addr,
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+ resource_size(entry->res));
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+ index++;
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+ }
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+ }
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems);
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--- a/drivers/pci/controller/plda/pcie-plda.h
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+++ b/drivers/pci/controller/plda/pcie-plda.h
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@@ -126,4 +126,9 @@ struct plda_pcie_rp {
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void __iomem *bridge_addr;
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};
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+void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
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+ phys_addr_t axi_addr, phys_addr_t pci_addr,
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+ size_t size);
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+int plda_pcie_setup_iomems(struct pci_host_bridge *bridge,
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+ struct plda_pcie_rp *port);
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#endif
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