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22d982ea00
On some devices the flash chip needs to be in 3-byte addressing mode during reboot, otherwise the boot loader will fail to start. This mode however does not allow regular reads/writes onto the upper 16M half. W25Q256 has separate read commands for reading from >16M, however it does not have any separate write commands. This patch changes the code to leave the chip in 3-byte mode most of the time and only switch during erase/write cycles that go to >16M addresses. Signed-off-by: Felix Fietkau <nbd@nbd.name>
125 lines
3.0 KiB
Diff
125 lines
3.0 KiB
Diff
--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -1453,6 +1453,67 @@ write_err:
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return ret;
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}
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+static int spi_nor_chunked_write(struct mtd_info *mtd, loff_t _to, size_t _len,
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+ size_t *_retlen, const u_char *_buf)
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+{
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+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
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+ u32 addr_width = nor->addr_width + !!(nor->flags & SNOR_F_4B_EXT_ADDR);
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+ int chunk_size;
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+ int retlen = 0;
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+ int ret;
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+
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+ chunk_size = nor->chunk_size;
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+ if (!chunk_size)
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+ chunk_size = _len;
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+
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+ if (addr_width > 3)
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+ chunk_size -= addr_width - 3;
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+
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+ while (retlen < _len) {
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+ size_t len = min_t(int, chunk_size, _len - retlen);
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+ const u_char *buf = _buf + retlen;
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+ loff_t to = _to + retlen;
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+
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+ if (nor->flags & SNOR_F_SST)
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+ ret = sst_write(mtd, to, len, &retlen, buf);
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+ else
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+ ret = spi_nor_write(mtd, to, len, &retlen, buf);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ *_retlen += retlen;
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+ return 0;
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+}
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+
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+static int spi_nor_chunked_read(struct mtd_info *mtd, loff_t _from, size_t _len,
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+ size_t *_retlen, u_char *_buf)
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+{
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+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
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+ int chunk_size;
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+ int ret;
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+
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+ chunk_size = nor->chunk_size;
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+ if (!chunk_size)
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+ chunk_size = _len;
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+
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+ *_retlen = 0;
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+ while (*_retlen < _len) {
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+ size_t len = min_t(int, chunk_size, _len - *_retlen);
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+ u_char *buf = _buf + *_retlen;
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+ loff_t from = _from + *_retlen;
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+ int retlen = 0;
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+
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+ ret = spi_nor_read(mtd, from, len, &retlen, buf);
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+ if (ret)
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+ return ret;
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+
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+ *_retlen += retlen;
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+ }
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+
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+ return 0;
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+}
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+
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static int macronix_quad_enable(struct spi_nor *nor)
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{
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int ret, val;
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@@ -1702,10 +1763,12 @@ int spi_nor_scan(struct spi_nor *nor, co
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}
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/* sst nor chips use AAI word program */
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- if (info->flags & SST_WRITE)
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+ if (info->flags & SST_WRITE) {
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mtd->_write = sst_write;
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- else
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+ nor->flags |= SNOR_F_SST;
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+ } else {
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mtd->_write = spi_nor_write;
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+ }
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if (info->flags & USE_FSR)
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nor->flags |= SNOR_F_USE_FSR;
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@@ -1735,11 +1798,20 @@ int spi_nor_scan(struct spi_nor *nor, co
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mtd->writebufsize = nor->page_size;
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if (np) {
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+ u32 val;
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+
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/* If we were instantiated by DT, use it */
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if (of_property_read_bool(np, "m25p,fast-read"))
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nor->flash_read = SPI_NOR_FAST;
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else
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nor->flash_read = SPI_NOR_NORMAL;
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+
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+ if (!of_property_read_u32(np, "m25p,chunked-io", &val)) {
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+ dev_info(dev, "using chunked io (size=%d)\n", val);
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+ mtd->_read = spi_nor_chunked_read;
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+ mtd->_write = spi_nor_chunked_write;
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+ nor->chunk_size = val;
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+ }
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} else {
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/* If we weren't instantiated by DT, default to fast-read */
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nor->flash_read = SPI_NOR_FAST;
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -143,6 +143,7 @@ enum spi_nor_option_flags {
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SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
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SNOR_F_READY_XSR_RDY = BIT(4),
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SNOR_F_4B_EXT_ADDR = BIT(5),
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+ SNOR_F_SST = BIT(6),
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};
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/**
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@@ -182,6 +183,7 @@ struct spi_nor {
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struct mutex lock;
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struct device *dev;
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u32 page_size;
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+ u16 chunk_size;
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u8 addr_width;
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u8 erase_opcode;
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u8 read_opcode;
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