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Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 70887a91ef710cada7d43ac2ec93280bb53d540f Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Wed, 13 Apr 2022 16:22:49 +0200
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Subject: [PATCH] drm/vc4: kms: Use maximum FIFO load for the HVS clock
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rate
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The core clock computation takes into account both the load due to the
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input (ie, planes) and its output (ie, encoders).
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However, while the input load needs to consider all the planes, and thus
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sum all of their associated loads, the output happens mostly in
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parallel.
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Therefore, we need to consider only the maximum of all the output loads,
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and not the sum like we were doing. This resulted in a clock rate way
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too high which could be discarded for being too high by the clock
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framework.
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Since recent changes, the clock framework will even downright reject it,
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leading to a core clock being too low for its current needs.
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Fixes: 16e101051f32 ("drm/vc4: Increase the core clock based on HVS load")
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_kms.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -939,7 +939,9 @@ vc4_core_clock_atomic_check(struct drm_a
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continue;
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num_outputs++;
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- cob_rate += hvs_new_state->fifo_state[i].fifo_load;
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+ cob_rate = max_t(unsigned long,
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+ hvs_new_state->fifo_state[i].fifo_load,
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+ cob_rate);
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}
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pixel_rate = load_state->hvs_load;
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