mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
3b88f74bbe
This backports some more patches from kernel 4.11 adding more devices to the device tree of the A64 SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
51 lines
1.5 KiB
Diff
51 lines
1.5 KiB
Diff
From a3e8f4926248b3c12933aacec4432e9b6de004bb Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Date: Mon, 9 Jan 2017 16:39:15 +0100
|
|
Subject: arm64: allwinner: a64: Add MMC pinctrl nodes
|
|
|
|
The A64 only has a single set of pins for each MMC controller. Since we
|
|
already have boards that require all of them, let's add them to the DTSI.
|
|
|
|
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
|
|
Acked-by: Chen-Yu Tsai <wens@csie.org>
|
|
---
|
|
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++++++++++++++++++++
|
|
1 file changed, 25 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
|
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
|
@@ -243,6 +243,31 @@
|
|
function = "i2c1";
|
|
};
|
|
|
|
+ mmc0_pins: mmc0-pins {
|
|
+ pins = "PF0", "PF1", "PF2", "PF3",
|
|
+ "PF4", "PF5";
|
|
+ function = "mmc0";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ mmc1_pins: mmc1-pins {
|
|
+ pins = "PG0", "PG1", "PG2", "PG3",
|
|
+ "PG4", "PG5";
|
|
+ function = "mmc1";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ mmc2_pins: mmc2-pins {
|
|
+ pins = "PC1", "PC5", "PC6", "PC8", "PC9",
|
|
+ "PC10","PC11", "PC12", "PC13",
|
|
+ "PC14", "PC15", "PC16";
|
|
+ function = "mmc2";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
uart0_pins_a: uart0@0 {
|
|
pins = "PB8", "PB9";
|
|
function = "uart0";
|