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64 lines
1.3 KiB
Plaintext
64 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* D-Link DWR-961 A1 Board Description
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* Copyright 2022 Pawel Dembicki <paweldembicki@gmail.com>
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*/
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#include "mt7620a_dlink_dwr-96x.dtsi"
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/ {
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compatible = "dlink,dwr-961-a1", "ralink,mt7620a-soc";
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model = "D-Link DWR-961 A1";
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leds {
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hidden-1 { /* hidden next to wlan5g led */
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label = "green:hidden-1";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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};
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hidden-2 { /* hidden next to sms led*/
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label = "green:hidden-2";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &mdio_pins>;
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port@5 {
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status = "okay";
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phy-mode = "rgmii";
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mediatek,fixed-link = <1000 1 1 1>;
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};
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mdio-bus {
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status = "okay";
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ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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qca,ar8327-initvals = <
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0x04 0x87300000 /* PORT0 PAD MODE CTRL */
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0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
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0x7c 0x0000007e /* PORT0_STATUS */
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0x80 0x00001200 /* PORT1_STATUS */
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0x84 0x00001200 /* PORT2_STATUS */
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0x88 0x00001200 /* PORT3_STATUS */
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0x8c 0x00001200 /* PORT4_STATUS */
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0x90 0x00001200 /* PORT5_STATUS */
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0x94 0x00000000 /* PORT6_STATUS */
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>;
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};
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};
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};
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&gsw {
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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&wifi {
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nvmem-cells = <&eeprom_config_e29e>, <&macaddr_config_e50e 2>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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