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215c1d05b8
Bump the 17.01 tree kernel to 4.4.69. Trunk 4.4 and 17.01 4.4 have diverged, talked this through with jow, he was okay with a clean diff against 17.01 and not a backported trunk patch. The following patches were applied upstream: * 062-[1-6]-MIPS-* series * 042-0004-mtd-bcm47xxpart-fix-parsing-first-block Reintroduced lantiq/patches-4.4/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup, as it was incorrectly included upstream thus dropped from LEDE, but subsequently reverted upstream. Thanks to Kevin Darbyshire-Bryant for pointing me to it. Compile-tested on: ar71xx, ramips/mt7621, x86/64. Run-tested on: ar71xx, ramips/mt7621, x86/64. Signed-off-by: Stijn Segers <francesco.borromini@inventati.org>
48 lines
2.1 KiB
Diff
48 lines
2.1 KiB
Diff
From 7bec0200ac214b5cba44e2c2c4385815be4b9f00 Mon Sep 17 00:00:00 2001
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From: Reinder de Haan <patchesrdh@mveas.com>
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Date: Sun, 15 Nov 2015 20:46:13 +0100
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Subject: [PATCH] clk: sunxi: Add support for the H3 usb phy clocks
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The H3 has a usb-phy clk register which is similar to that of earlier
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SoCs, but with support for a larger number of phys. So we can simply add
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a new set of clk-data and a new compatible and be done with it.
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Acked-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
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drivers/clk/sunxi/clk-usb.c | 12 ++++++++++++
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2 files changed, 13 insertions(+)
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -70,6 +70,7 @@ Required properties:
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"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
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"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
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"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
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+ "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
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"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
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"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
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--- a/drivers/clk/sunxi/clk-usb.c
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+++ b/drivers/clk/sunxi/clk-usb.c
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@@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_set
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sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
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}
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CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
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+
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+static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
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+ .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
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+ BIT(11) | BIT(10) | BIT(9) | BIT(8),
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+ .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
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+};
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+
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+static void __init sun8i_h3_usb_setup(struct device_node *node)
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+{
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+ sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
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+}
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+CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);
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