mirror of
https://github.com/openwrt/openwrt.git
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9af0e94fa6
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.64
Manually rebased:
generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
bcm27xx/patches-6.6/950-0585-drm-vc4-Introduce-generation-number-enum.patch
bcm27xx/patches-6.6/950-0610-drm-vc4-hvs-Support-BCM2712-HVS.patch
bcm27xx/patches-6.6/950-0829-vc4-hvs-Add-support-for-D0-register-changes.patch
Removed upstreamed:
bcm27xx/patches-6.6/950-0597-drm-vc4-hdmi-Avoid-hang-with-debug-registers-when-su.patch[1]
bcm27xx/patches-6.6/950-0599-drm-vc4-Fix-dlist-debug-not-resetting-the-next-entry.patch[2]
bcm27xx/patches-6.6/950-0600-drm-vc4-Remove-incorrect-limit-from-hvs_dlist-debugf.patch[3]
bcm27xx/patches-6.6/950-0708-drm-vc4-Correct-logic-on-stopping-an-HVS-channel.patch[4]
ramips/patches-6.6/002-01-v6.13-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT38.patch[5]
ramips/patches-6.6/002-02-v6.13-clk-ralink-mtmips-fix-clocks-probe-order-in-oldest-r.patch[6]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=223ee2567a55e4f80315c768d2969e6a3b9fb23d
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=8182b5ca19c6f173b6498d1c6d3e4b034b76bbde
3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=52c1716f65a558174e381360bd88f18dae4be85c
4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=9728b508b01a5eeeac79ceb676364c674dd951ac
5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=f85a1d06afbcc57ac44176db8f9d7a934979952c
6. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=fbb13732c6ffa9d58cedafabcd5ce8fd7ef8ae5a
Build system: x86/64
Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/17217
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 5158e28769)
65 lines
2.2 KiB
Diff
65 lines
2.2 KiB
Diff
From 62bc808af174dfc9365ae54cbaf6c21f662ea4c3 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Wed, 4 Oct 2023 16:02:39 +0100
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Subject: [PATCH 0655/1085] vc4/drm: Remove the clear of SCALER_DISPBKGND_FILL
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Since "drm/vc4: hvs: Support BCM2712 HVS" booting Pi4
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with dual 4kp30 displays connected fails with:
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vc4-drm gpu: [drm] *ERROR* [CRTC:107:pixelvalve-4] flip_done timed out
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It has been tracked down to the referenced commit adding a
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path to clear the SCALER_DISPBKGND_FILL when not required.
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Dual 4kp30 works with a core clock of 297MHz when background fill
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is enabled, but requires a higher value with it disabled.
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320MHz still fails, while 330MHz seems okay.
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Lets always enable background fill for Pi0-4.
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Fixes: e84da235223d ("drm/vc4: hvs: Support BCM2712 HVS")
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 20 +++++++++-----------
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1 file changed, 9 insertions(+), 11 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -1305,27 +1305,25 @@ void vc4_hvs_atomic_flush(struct drm_crt
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WARN_ON(!vc4_state->mm);
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WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm->mm_node.size);
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- if (enable_bg_fill) {
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+ if (vc4->gen >= VC4_GEN_6) {
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/* This sets a black background color fill, as is the case
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* with other DRM drivers.
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*/
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- if (vc4->gen >= VC4_GEN_6)
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+ if (enable_bg_fill)
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HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
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HVS_READ(SCALER6_DISPX_CTRL1(channel)) |
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SCALER6_DISPX_CTRL1_BGENB);
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else
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- HVS_WRITE(SCALER_DISPBKGNDX(channel),
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- HVS_READ(SCALER_DISPBKGNDX(channel)) |
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- SCALER_DISPBKGND_FILL);
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- } else {
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- if (vc4->gen >= VC4_GEN_6)
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HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
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HVS_READ(SCALER6_DISPX_CTRL1(channel)) &
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~SCALER6_DISPX_CTRL1_BGENB);
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- else
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- HVS_WRITE(SCALER_DISPBKGNDX(channel),
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- HVS_READ(SCALER_DISPBKGNDX(channel)) &
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- ~SCALER_DISPBKGND_FILL);
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+ } else {
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+ /* we can actually run with a lower core clock when background
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+ * fill is enabled on VC4_GEN_5 so leave it enabled always.
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+ */
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+ HVS_WRITE(SCALER_DISPBKGNDX(channel),
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+ HVS_READ(SCALER_DISPBKGNDX(channel)) |
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+ SCALER_DISPBKGND_FILL);
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}
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/* Only update DISPLIST if the CRTC was already running and is not
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