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https://github.com/openwrt/openwrt.git
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9af0e94fa6
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.64
Manually rebased:
generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
bcm27xx/patches-6.6/950-0585-drm-vc4-Introduce-generation-number-enum.patch
bcm27xx/patches-6.6/950-0610-drm-vc4-hvs-Support-BCM2712-HVS.patch
bcm27xx/patches-6.6/950-0829-vc4-hvs-Add-support-for-D0-register-changes.patch
Removed upstreamed:
bcm27xx/patches-6.6/950-0597-drm-vc4-hdmi-Avoid-hang-with-debug-registers-when-su.patch[1]
bcm27xx/patches-6.6/950-0599-drm-vc4-Fix-dlist-debug-not-resetting-the-next-entry.patch[2]
bcm27xx/patches-6.6/950-0600-drm-vc4-Remove-incorrect-limit-from-hvs_dlist-debugf.patch[3]
bcm27xx/patches-6.6/950-0708-drm-vc4-Correct-logic-on-stopping-an-HVS-channel.patch[4]
ramips/patches-6.6/002-01-v6.13-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT38.patch[5]
ramips/patches-6.6/002-02-v6.13-clk-ralink-mtmips-fix-clocks-probe-order-in-oldest-r.patch[6]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=223ee2567a55e4f80315c768d2969e6a3b9fb23d
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=8182b5ca19c6f173b6498d1c6d3e4b034b76bbde
3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=52c1716f65a558174e381360bd88f18dae4be85c
4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=9728b508b01a5eeeac79ceb676364c674dd951ac
5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=f85a1d06afbcc57ac44176db8f9d7a934979952c
6. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.64&id=fbb13732c6ffa9d58cedafabcd5ce8fd7ef8ae5a
Build system: x86/64
Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3
Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/17217
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 5158e28769)
51 lines
1.9 KiB
Diff
51 lines
1.9 KiB
Diff
From 66372055ffda939ce52ddc64270079dd4f04d764 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Fri, 21 Apr 2023 22:00:16 +0100
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Subject: [PATCH 0468/1085] drm/vc4: hdmi: Increase MAI fifo dreq threshold
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Now we wait for write responses and have a burst
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size of 4, we can set the fifo threshold much higher.
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Set it to 28 (of the 32 entry size) to keep fifo
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fuller and reduce chance of underflow.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 18 +++++++++++++-----
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1 file changed, 13 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -2531,6 +2531,7 @@ static int vc4_hdmi_audio_prepare(struct
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{
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struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
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struct drm_device *drm = vc4_hdmi->connector.dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(drm);
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struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
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unsigned int sample_rate = params->sample_rate;
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unsigned int channels = params->channels;
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@@ -2589,11 +2590,18 @@ static int vc4_hdmi_audio_prepare(struct
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VC4_HDMI_AUDIO_PACKET_CEA_MASK);
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/* Set the MAI threshold */
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- HDMI_WRITE(HDMI_MAI_THR,
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- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
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- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
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- VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
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- VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
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+ if (vc4->is_vc5)
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+ HDMI_WRITE(HDMI_MAI_THR,
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+ VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
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+ VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
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+ VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
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+ VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
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+ else
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+ HDMI_WRITE(HDMI_MAI_THR,
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+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
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+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
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+ VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
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+ VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
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HDMI_WRITE(HDMI_MAI_CONFIG,
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VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
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