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20ea6adbf1
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
189 lines
6.6 KiB
Diff
189 lines
6.6 KiB
Diff
From 8f32ff08609bb5e7fd4fb38fe7518891e0e22f45 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Wed, 10 Feb 2021 18:46:22 +0000
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Subject: [PATCH] drm/vc4: Fix dsi0 interrupt support.
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DSI0 seemingly had very little or no testing as a load of
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the register mappings were incorrect/missing, so host
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transfers always timed out due to enabling/checking incorrect
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bits in the interrupt enable and status registers.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 111 ++++++++++++++++++++++++++--------
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1 file changed, 85 insertions(+), 26 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -181,8 +181,50 @@
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#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
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-#define DSI0_INT_STAT 0x24
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-#define DSI0_INT_EN 0x28
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+#define DSI0_INT_STAT 0x24
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+#define DSI0_INT_EN 0x28
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+# define DSI0_INT_FIFO_ERR BIT(25)
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+# define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23)
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+# define DSI0_INT_CMDC_DONE_SHIFT 23
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+# define DSI0_INT_CMDC_DONE_NO_REPEAT 1
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+# define DSI0_INT_CMDC_DONE_REPEAT 3
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+# define DSI0_INT_PHY_DIR_RTF BIT(22)
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+# define DSI0_INT_PHY_D1_ULPS BIT(21)
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+# define DSI0_INT_PHY_D1_STOP BIT(20)
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+# define DSI0_INT_PHY_RXLPDT BIT(19)
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+# define DSI0_INT_PHY_RXTRIG BIT(18)
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+# define DSI0_INT_PHY_D0_ULPS BIT(17)
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+# define DSI0_INT_PHY_D0_LPDT BIT(16)
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+# define DSI0_INT_PHY_D0_FTR BIT(15)
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+# define DSI0_INT_PHY_D0_STOP BIT(14)
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+/* Signaled when the clock lane enters the given state. */
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+# define DSI0_INT_PHY_CLK_ULPS BIT(13)
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+# define DSI0_INT_PHY_CLK_HS BIT(12)
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+# define DSI0_INT_PHY_CLK_FTR BIT(11)
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+/* Signaled on timeouts */
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+# define DSI0_INT_PR_TO BIT(10)
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+# define DSI0_INT_TA_TO BIT(9)
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+# define DSI0_INT_LPRX_TO BIT(8)
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+# define DSI0_INT_HSTX_TO BIT(7)
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+/* Contention on a line when trying to drive the line low */
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+# define DSI0_INT_ERR_CONT_LP1 BIT(6)
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+# define DSI0_INT_ERR_CONT_LP0 BIT(5)
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+/* Control error: incorrect line state sequence on data lane 0. */
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+# define DSI0_INT_ERR_CONTROL BIT(4)
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+# define DSI0_INT_ERR_SYNC_ESC BIT(3)
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+# define DSI0_INT_RX2_PKT BIT(2)
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+# define DSI0_INT_RX1_PKT BIT(1)
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+# define DSI0_INT_CMD_PKT BIT(0)
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+
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+#define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \
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+ DSI0_INT_ERR_CONTROL | \
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+ DSI0_INT_ERR_CONT_LP0 | \
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+ DSI0_INT_ERR_CONT_LP1 | \
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+ DSI0_INT_HSTX_TO | \
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+ DSI0_INT_LPRX_TO | \
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+ DSI0_INT_TA_TO | \
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+ DSI0_INT_PR_TO)
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+
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# define DSI1_INT_PHY_D3_ULPS BIT(30)
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# define DSI1_INT_PHY_D3_STOP BIT(29)
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# define DSI1_INT_PHY_D2_ULPS BIT(28)
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@@ -894,6 +936,9 @@ static void vc4_dsi_encoder_enable(struc
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DSI_PORT_WRITE(PHY_AFEC0, afec0);
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+ /* AFEC reset hold time */
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+ mdelay(1);
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+
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DSI_PORT_WRITE(PHY_AFEC1,
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VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
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VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
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@@ -1060,12 +1105,9 @@ static void vc4_dsi_encoder_enable(struc
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DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
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/* Bring AFE out of reset. */
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- if (dsi->variant->port == 0) {
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- } else {
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- DSI_PORT_WRITE(PHY_AFEC0,
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- DSI_PORT_READ(PHY_AFEC0) &
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- ~DSI1_PHY_AFEC0_RESET);
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- }
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+ DSI_PORT_WRITE(PHY_AFEC0,
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+ DSI_PORT_READ(PHY_AFEC0) &
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+ ~DSI_PORT_BIT(PHY_AFEC0_RESET));
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vc4_dsi_ulps(dsi, false);
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@@ -1184,13 +1226,28 @@ static ssize_t vc4_dsi_host_transfer(str
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/* Enable the appropriate interrupt for the transfer completion. */
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dsi->xfer_result = 0;
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reinit_completion(&dsi->xfer_completion);
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- DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
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- if (msg->rx_len) {
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- DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
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- DSI1_INT_PHY_DIR_RTF));
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+ if (dsi->variant->port == 0) {
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+ DSI_PORT_WRITE(INT_STAT,
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+ DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);
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+ if (msg->rx_len) {
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+ DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |
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+ DSI0_INT_PHY_DIR_RTF));
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+ } else {
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+ DSI_PORT_WRITE(INT_EN,
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+ (DSI0_INTERRUPTS_ALWAYS_ENABLED |
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+ VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,
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+ DSI0_INT_CMDC_DONE)));
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+ }
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} else {
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- DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
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- DSI1_INT_TXPKT1_DONE));
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+ DSI_PORT_WRITE(INT_STAT,
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+ DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
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+ if (msg->rx_len) {
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+ DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
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+ DSI1_INT_PHY_DIR_RTF));
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+ } else {
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+ DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
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+ DSI1_INT_TXPKT1_DONE));
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+ }
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}
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/* Send the packet. */
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@@ -1207,7 +1264,7 @@ static ssize_t vc4_dsi_host_transfer(str
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ret = dsi->xfer_result;
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}
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- DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
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+ DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
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if (ret)
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goto reset_fifo_and_return;
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@@ -1253,7 +1310,7 @@ reset_fifo_and_return:
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DSI_PORT_BIT(CTRL_RESET_FIFOS));
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DSI_PORT_WRITE(TXPKT1C, 0);
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- DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
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+ DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
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return ret;
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}
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@@ -1390,26 +1447,28 @@ static irqreturn_t vc4_dsi_irq_handler(i
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DSI_PORT_WRITE(INT_STAT, stat);
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
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+ DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
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+ DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_ERR_CONT_LP0, "LP0 contention");
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+ DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_ERR_CONT_LP1, "LP1 contention");
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+ DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_HSTX_TO, "HSTX timeout");
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+ DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_LPRX_TO, "LPRX timeout");
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+ DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_TA_TO, "turnaround timeout");
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+ DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");
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dsi_handle_error(dsi, &ret, stat,
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- DSI1_INT_PR_TO, "peripheral reset timeout");
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+ DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");
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- if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
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+ if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
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+ DSI0_INT_CMDC_DONE_MASK) |
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+ DSI_PORT_BIT(INT_PHY_DIR_RTF))) {
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complete(&dsi->xfer_completion);
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ret = IRQ_HANDLED;
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- } else if (stat & DSI1_INT_HSTX_TO) {
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+ } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {
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complete(&dsi->xfer_completion);
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dsi->xfer_result = -ETIMEDOUT;
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ret = IRQ_HANDLED;
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