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f003d732d7
Refreshed all patches. Removed upstreamed: - 031-v5.0-MIPS-BCM47XX-Setup-struct-device-for-the-SoC.patch - 142-jffs2-Fix-use-of-uninitialized-delayed_work-lockdep-.patch Removed upstreamed hunk in: - 800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
142 lines
4.8 KiB
Diff
142 lines
4.8 KiB
Diff
From ce81398dccb984855de606b75db25eddecdaa9e5 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Wed, 10 Oct 2018 20:25:39 +0200
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Subject: [PATCH 02/18] pinctrl: gemini: Fix up TVC clock group
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The previous fix made the TVC clock get muxed in on the
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D-Link DIR-685 instead of giving nagging warnings of this
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not working. Not good. We didn't want that, as it breaks
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video.
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Create a specific group for the TVC CLK, and break out
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a specific GPIO group for it on the SL3516 so we can use
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that line as GPIO if we don't need the TVC CLK.
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Fixes: d17f477c5bc6 ("pinctrl: gemini: Mask and set properly")
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/pinctrl-gemini.c | 44 ++++++++++++++++++++++++++------
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1 file changed, 36 insertions(+), 8 deletions(-)
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--- a/drivers/pinctrl/pinctrl-gemini.c
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+++ b/drivers/pinctrl/pinctrl-gemini.c
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@@ -591,13 +591,16 @@ static const unsigned int tvc_3512_pins[
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319, /* TVC_DATA[1] */
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301, /* TVC_DATA[2] */
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283, /* TVC_DATA[3] */
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- 265, /* TVC_CLK */
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320, /* TVC_DATA[4] */
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302, /* TVC_DATA[5] */
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284, /* TVC_DATA[6] */
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266, /* TVC_DATA[7] */
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};
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+static const unsigned int tvc_clk_3512_pins[] = {
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+ 265, /* TVC_CLK */
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+};
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+
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/* NAND flash pins */
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static const unsigned int nflash_3512_pins[] = {
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199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
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@@ -629,7 +632,7 @@ static const unsigned int pflash_3512_pi
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/* Serial flash pins CE0, CE1, DI, DO, CK */
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static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
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-/* The GPIO0A (0) pin overlap with TVC and extended parallel flash */
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+/* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */
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static const unsigned int gpio0a_3512_pins[] = { 265 };
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/* The GPIO0B (1-4) pins overlap with TVC and ICE */
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@@ -823,7 +826,13 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(tvc_3512_pins),
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/* Conflict with character LCD and ICE */
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.mask = LCD_PADS_ENABLE,
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- .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
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+ .value = TVC_PADS_ENABLE,
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+ },
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+ {
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+ .name = "tvcclkgrp",
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+ .pins = tvc_clk_3512_pins,
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+ .num_pins = ARRAY_SIZE(tvc_clk_3512_pins),
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+ .value = TVC_CLK_PAD_ENABLE,
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},
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/*
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* The construction is done such that it is possible to use a serial
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@@ -860,8 +869,8 @@ static const struct gemini_pin_group gem
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.name = "gpio0agrp",
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.pins = gpio0a_3512_pins,
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.num_pins = ARRAY_SIZE(gpio0a_3512_pins),
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- /* Conflict with TVC */
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- .mask = TVC_PADS_ENABLE,
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+ /* Conflict with TVC CLK */
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+ .mask = TVC_CLK_PAD_ENABLE,
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},
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{
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.name = "gpio0bgrp",
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@@ -1531,13 +1540,16 @@ static const unsigned int tvc_3516_pins[
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311, /* TVC_DATA[1] */
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394, /* TVC_DATA[2] */
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374, /* TVC_DATA[3] */
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- 333, /* TVC_CLK */
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354, /* TVC_DATA[4] */
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395, /* TVC_DATA[5] */
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312, /* TVC_DATA[6] */
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334, /* TVC_DATA[7] */
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};
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+static const unsigned int tvc_clk_3516_pins[] = {
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+ 333, /* TVC_CLK */
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+};
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+
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/* NAND flash pins */
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static const unsigned int nflash_3516_pins[] = {
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243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
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@@ -1570,7 +1582,7 @@ static const unsigned int pflash_3516_pi
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static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
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/* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
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-static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 };
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+static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 };
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/* The GPIO0B (5-7) pins overlap with ICE */
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static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
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@@ -1602,6 +1614,9 @@ static const unsigned int gpio0j_3516_pi
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/* The GPIO0K (30,31) pins overlap with NAND flash */
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static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
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+/* The GPIO0L (0) pins overlap with TVC_CLK */
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+static const unsigned int gpio0l_3516_pins[] = { 333 };
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+
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/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
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static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
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@@ -1761,7 +1776,13 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(tvc_3516_pins),
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/* Conflict with character LCD */
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.mask = LCD_PADS_ENABLE,
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- .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
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+ .value = TVC_PADS_ENABLE,
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+ },
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+ {
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+ .name = "tvcclkgrp",
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+ .pins = tvc_clk_3516_pins,
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+ .num_pins = ARRAY_SIZE(tvc_clk_3516_pins),
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+ .value = TVC_CLK_PAD_ENABLE,
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},
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/*
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* The construction is done such that it is possible to use a serial
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@@ -1873,6 +1894,13 @@ static const struct gemini_pin_group gem
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.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
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},
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{
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+ .name = "gpio0lgrp",
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+ .pins = gpio0l_3516_pins,
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+ .num_pins = ARRAY_SIZE(gpio0l_3516_pins),
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+ /* Conflict with TVE CLK */
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+ .mask = TVC_CLK_PAD_ENABLE,
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+ },
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+ {
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.name = "gpio1agrp",
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.pins = gpio1a_3516_pins,
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.num_pins = ARRAY_SIZE(gpio1a_3516_pins),
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