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1f818b09f8
This series of upstream patches properly implement a clock and reset driver for old ralink SoCs[1]. And it includes some related fixes[2] and improvements[3][4]. All patches have been merged into linux-next. They will be part of upcoming Linux 6.5. In order to switch to the new system controller driver, all clocks and resets properties in SoC dtsi have been updated, and kernel symbol "CONFIG_CLK_MTMIPS" have been added to the kernel config files. [1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com [2] https://lore.kernel.org/all/20230622-mips-ralink-clk-wuninitialized-v1-1-ea9041240d10@kernel.org [3] https://lore.kernel.org/all/OSYP286MB03120BABB25900E113ED42B7BC5CA@OSYP286MB0312.JPNP286.PROD.OUTLOOK.COM [4] https://lore.kernel.org/all/TYAP286MB03151148AF8C054621DD55C3BC23A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM Tested on Motorola MWR03 (MT7628) Tested on Haier HW-L1W (MT7620) Signed-off-by: Shiji Yang <yangshiji66@qq.com>
87 lines
2.6 KiB
Diff
87 lines
2.6 KiB
Diff
From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 19 Jun 2023 06:09:33 +0200
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Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
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Adds device tree binding documentation for system controller node present
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in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
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for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
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RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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.../bindings/clock/mediatek,mtmips-sysc.yaml | 64 ++++++++++++++++++++++
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1 file changed, 64 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
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@@ -0,0 +1,64 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MTMIPS SoCs System Controller
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+
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+maintainers:
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+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
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+
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+description: |
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+ MediaTek MIPS and Ralink SoCs provides a system controller to allow
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+ to access to system control registers. These registers include clock
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+ and reset related ones so this node is both clock and reset provider
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+ for the rest of the world.
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+
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+ These SoCs have an XTAL from where the cpu clock is
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+ provided as well as derived clocks for the bus and the peripherals.
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+
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+properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - ralink,mt7620-sysc
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+ - ralink,mt7628-sysc
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+ - ralink,mt7688-sysc
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+ - ralink,rt2880-sysc
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+ - ralink,rt3050-sysc
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+ - ralink,rt3052-sysc
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+ - ralink,rt3352-sysc
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+ - ralink,rt3883-sysc
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+ - ralink,rt5350-sysc
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+ - const: syscon
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+
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+ reg:
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+ maxItems: 1
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+
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+ '#clock-cells':
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+ description:
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+ The first cell indicates the clock number.
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+ const: 1
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+
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+ '#reset-cells':
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+ description:
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+ The first cell indicates the reset bit within the register.
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - '#clock-cells'
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+ - '#reset-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ syscon@0 {
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+ compatible = "ralink,rt5350-sysc", "syscon";
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+ reg = <0x0 0x100>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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